Carbon nanotubes (CNTs) have unique properties with promise to outperform the electrical characteristics of bulk copper, giving rise to its primary driver for use in electronic devices. The challenge still hindering their full exploitation stems from an inability to manufacture them to long lengths, resulting in a requirement to align and entwine them into a yarn or wire. There have been several methods presented in achieving this, however, the common disadvantage has been that they are only applicable to specific types and morphologies of CNTs. In the work reported here, using electrospinning as a universally applicable route for any CNT type, we re-engineer and optimise the various formulation, fabrication and processing steps required to manufacture CNT wires. Through a series of investigations using a materials agnostic approach, we experimentally probe the choice of solvent, surfactant and thermal treatment temperature of the CNT inks, demonstrating the CNT-type optimum using a range of commercially available single- double- and multiwalled CNTs. Finally, this allowed us to develop and probe an electrical conditioning process to further enhance the electrical performance, achieving the highest reported un-doped electrical conductivity of 36,000 S⋅m− 1 for electrospun CNT wires, or a specific conductivity of 0.2×106S·m−1/g·cm−3. [Display omitted]
Research into carbon nanotubes (CNTs) has been a hot topic for almost 3 decades, and it is now that we are beginning to observe the impact of advanced applictions of this nanomaterial in areas such as electronics. Currently, in order to mass produce CNT devices, either large-scale synthesis, followed by numerous energy-intensive processing steps or photolithography processes, including several sputter-deposition steps, are required to pattern this material to fabricate functional devices. In the work reported here, through the utilization of a universal catalyst precursor (cyclopentadienyl iron dicarbonyl dimer) and the optimization of solution parameters, patterned high-quality vertically aligned arrays of single- and few-walled CNTs have been synthesized via various inexpensive, commercially scalable methods such as inkjet printing, stamp printing, spray painting, and even handwriting. The two-step process of precursor printing, followed immediately by CNT growth, results in CNTs with a Raman I-D/I-G ratio of 0.073, demonstrating very high-quality nanotubes. This process eliminates time-consuming and costly CNT post processing techniques or the deposition of numerous substrate barrier and catalyst layers to achieve device manufacturing. As a result, this method has the potential to provide a route for the large-scale synthesis of high-quality single- and few-walled CNTs that can be applied in industrial settings.
Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.