Dr Radu Sporea

Research Interests

Current research focuses on power-efficient, cost-effective large-area electronics in organic and inorganic semiconductor technologies. Most of the work is based on the concept of source-gated transistor(SGT), a device invented at Surrey by Prof Shannon and collaborators.

Previous results in polysilicon and amorphous silicon devices highlight the performance benefits of SGTs: higher amplification and lower energy requirements in certain circuit configurations.

Now, using solution-processed semiconductor technologies we aim to create large-area flexible and possibly transparent electronic circuits which are very resilient to process variations and can be made without the complex tools required by conventional material deposition and photolithography processes. 

We rely on Dimatix ink jet printing of conductive nanoparticle inks, semiconducting polymers or small molecules and insulators to create organic transistors (OFET and OSGT) and circuits on a variety of inexpensive transparent and flexible substrates such as PEN or PET.

The flip side of the research activity is represented by computer simulation and modelling of device physics and circuit design using the SILVACO suite (Atlas, Athena, MixedMode) for analog and mixed signal applications.

Research Collaborations

Shanghai Jiao Tong University, China

Welsh Centre for Printing and Coating, UK

Digital World Research Centre, University of Surrey, UK

Teaching

Teaching modules:

EEE1026 - Engineering Science I

EEE1027 - First year undergraduate EEE labs

EEE2042- Electronic and Photonic Devices

PhD, MSc, summer placement and UG projects

Projects are available in the following areas:

  • Reliability, performance and fabrication of electronic devices and circuits
  • Organic and inorganic advanced devices and circuits
  • Energy-efficient electronic devices and circuits
  • Simulation and modelling of semiconductor device physics
  • Simulation and modelling of electronic circuits

Departmental Duties

  • Early career researcher representative
  • Public engagement and outreach in Engineering
  • Headstart summer school co-ordinator
  • Undergraduate final year project supervision
  • Nuffield/SATRO Research Placement host
  • EE Athena Swan committee

Affiliations

IEEE
Secretary of UK and Ireland committee, Society for Information Display, SID
The Electrochemical Society - ECS
The Institution of Engineering and Technology - IET

Technical Program Committee member for ESSDERC
Technical Program Committee member for ITC
Technical Program Committee member for CAD-TFT

Awards

2014 – Impact Accelleration Account - £25,000

2013 – Santander Postgraduate Research Award with SJTU, China –£4,800

2012 – Santander Staff Mobility Award – £1,700
2012 – Santander Postgraduate Research Award with SJTU, China –£3,950

2011 – RAEng Academic Research Fellowship - £460,000

2010 – EPSRC PhD Plus - £48,000 

 

Public engagement in Science

Occasionally, Radu will write, present and produce short Science films, available on YouTube.

His Electronic Engineering podcast is hosted on Surrey EE Podcasts and has been featured on Pod Academy. Since 2014, Radu is the Academic Minute's resident technology expert.

Radu is available for school, evening and weekend talks and debates on:

  • History of electronic engineering
  • Impact of electronic and computer technology
  • The process of research in advanced technologies

 

Radu has organised and presented talks at Cheltenham and the British Science Festivals, and was awarded the I K Brunel Award and Lecture for Engineering and Technology by the British Science Association in 2015.

He has served as scientific advisor on the BBC Series “Shock and Awe: The Story of Electricity” presented by Surrey’s Prof Jim Al-Khalili.

Radu was a participant in the 2012 edition of Famelab.

 

Radu has performed on and presented at Café Scientifique, Science Showoff, Bright Club and Pecha Kucha Guildford.
He appeared on BBC4's "Some Boffins with Jokes" wearing the same outfit! 

Contact Me

E-mail:
Phone: 01483 68 6086

Find me on campus
Room: 27 ATI 02


My office hours

Student meetings by appointment and Thursdays 12.30-1.45

Publications

Journal articles

  • Sporea RA, Lygo-Baker S. (2016) 'Summer Research Placements - State-of-the-Art Science by pre-University Students'. MRS Advances, Article number MRSF15-2327286.R1
  • Dahiya AS, Opoku C, Sporea RA, Sarvankumar B, Poulin-Vittrant G, Cayrel F, Camara N, Alquier D. (2016) 'Single-crystalline ZnO sheet Source-Gated Transistors'. Nature Publishing Group Scientific Reports, 6 Article number 19232

    Abstract

    Due to their fabrication simplicity, fully compatible with low-cost large-area device assembly strategies, source-gated transistors (SGTs) have received significant research attention in the area of high-performance electronics over large area low-cost substrates. While usually based on either amorphous or polycrystalline silicon (α-Si and poly-Si, respectively) thin-film technologies, the present work demonstrate the assembly of SGTs based on single-crystalline ZnO sheet (ZS) with asymmetric ohmic drain and Schottky source contacts. Electrical transport studies of the fabricated devices show excellent field-effect transport behaviour with abrupt drain current saturation (IDSSAT) at low drain voltages well below 2 V, even at very large gate voltages. The performance of a ZS based SGT is compared with a similar device with ohmic source contacts. The ZS SGT is found to exhibit much higher intrinsic gain, comparable on/off ratio and low off currents in the sub-picoamp range. This approach of device assembly may form the technological basis for highly efficient low-power analog and digital electronics using ZnO and/or other semiconducting nanomaterial.

  • Opoku C, Sporea R, Stolojan V, Silva R, Shkunov M. (2015) 'Si Nanowire - Array Source Gated Transistors'.
  • Sporea RA, Burridge T, Silva SRP. (2015) 'Self-Heating Effects In Polysilicon Source Gated Transistors'. NATURE PUBLISHING GROUP SCIENTIFIC REPORTS, 5 Article number ARTN 14058
  • Sporea RA, Overy M, Shannon JM, Silva SRP. (2015) 'Temperature dependence of the current in Schottky-barrier source-gated transistors'. Journal of Applied Physics, 117 (18)
  • Sporea RA, Wright W, Shannon JM, Silva SRP. (2015) 'Bulk barrier source-gated transistors with improved drain current dynamic range and temperature coefficient'. ECS Transactions, 67 (1), pp. 91-96.
  • Cui Q, Sporea RA, Liu W, Guo X. (2014) 'Analytical models for delay and power analysis of zero-VGS load unipolar thin-film Transistor Logic Circuits'. IEEE Transactions on Electron Devices, 61 (11), pp. 3838-3844.
  • Cui Q, Sporea RA, Liu W, Guo X. (2014) 'Analytical Models for Delay and Power Analysis of Zero-[Formula: see text] Load Unipolar Thin-Film Transistor Logic Circuits'. IEEE Transactions on Electron Devices,
  • Sporea RA, Trainor MJ, Young ND, Shannon JM, Silva SR. (2014) 'Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits.'. Sci Rep, England: 4

    Abstract

    Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

  • Xu X, Sporea RA, Guo X. (2013) 'Source-Gated Transistors for Power- and Area-Efficient AMOLED Pixel Circuits'. IEEE Journal of Display Technology,
  • Sporea RA, Georgakopoulos S, Shkunov M, Shannon JM, Silva SRP, Xu X, Guo X. (2013) 'Leveraging contact effects for field-effect transistor technologies with reduced complexity and superior current uniformity'. International Review of the Red Cross, 1553 (888)
  • Sporea RA, Georgakopoulos S, Shkunov M, Shannon JM, Silva SRP, Xu X, Guo X. (2013) 'Leveraging contact effects for field-effect transistor technologies with reduced complexity and superior current uniformity'. MRS Online Proceedings Library, 1553

    Abstract

    In order to achieve high performance, the design of devices for large-area electronics needs to be optimized despite material or fabrication shortcomings. In numerous emerging technologies thin-film transistor (TFT) performance is hindered by contact effects. Here, we show that contact effects can be used constructively to create devices with performance characteristics unachievable by conventional transistor designs. Source-gated transistors (SGTs) are not designed with increasing transistor speed, mobility or sub-threshold slope in mind, but rather with improving certain aspects critical for real-world large area electronics such as stability, uniformity, power efficiency and gain. SGTs can achieve considerably lower saturation voltage and power dissipation compared to conventional devices driven at the same current; higher output impedance for over two orders of magnitude higher intrinsic gain; improved bias stress stability in amorphous materials; higher resilience to processing variations; current virtually independent of source-drain gap, source-gate overlap and semiconductor thickness variations. Applications such as amplifiers and drivers for sensors and actuators, low cost large area analog or digital circuits could greatly benefit from incorporating the SGT architecture.

  • Shannon JM, Sporea RA, Georgakopoulos S, Shkunov M, Silva SRP. (2013) 'Low-Field Behavior of Source-Gated Transistors'. IEEE IEEE Transactions on Electron Devices, 60 (8), pp. 2444-2449.

    Abstract

    A physical description of low-field behavior of a Schottky source-gated transistor (SGT) is outlined where carriers crossing the source barrier by thermionic emission are restricted by JFET action in the pinch-off region at the drain end of the source. This mode of operation leads to transistor characteristics with low saturation voltage and high output impedance without the need for field relief at the edge of the Schottky source barrier and explains many characteristics of SGT observed experimentally. 2-D device simulations with and without barrier lowering due to the Schottky effect show that the transistors can be designed so that the current is independent of source length and thickness variations in the semiconductor. This feature together with the fact that the current in an SGT is independent of source-drain separation hypothesizes the fabrication of uniform current sources and other large-area analog circuit blocks with repeatable performance even in imprecise technologies such as high-speed printing.

  • Shannon JM, Sporea RA, Georgakopoulos S, Shkunov M, Silva SRP. (2013) 'Low-Field Behavior of Source-Gated Transistors'. IEEE Transactions on Electron Devices,

    Abstract

    A physical description of low-field behavior of a Schottky source-gated transistor (SGT) is outlined where carriers crossing the source barrier by thermionic emission are restricted by JFET action in the pinch-off region at the drain end of the source. This mode of operation leads to transistor characteristics with low saturation voltage and high output impedance without the need for field relief at the edge of the Schottky source barrier and explains many characteristics of SGT observed experimentally. 2-D device simulations with and without barrier lowering due to the Schottky effect show that the transistors can be designed so that the current is independent of source length and thickness variations in the semiconductor. This feature together with the fact that the current in an SGT is independent of source-drain separation hypothesizes the fabrication of uniform current sources and other large-area analog circuit blocks with repeatable performance even in imprecise technologies such as high-speed printing.

  • Cui Q, Si M, Sporea RA, Guo X. (2013) 'Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits'. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC IEEE TRANSACTIONS ON ELECTRON DEVICES, 60 (5), pp. 1782-1785.
  • Sporea RA, Alshammari AS, Georgakopoulos S, Underwood J, Shkunov M, Silva SRP. (2013) 'Micron-scale inkjet-assisted digital lithography for large-area flexible electronics'. European Solid-State Device Research Conference, , pp. 280-283.

    Abstract

    Large-area electronics require cost-effective yet precise patterning of electrodes. We demonstrate a simple electrode patterning technique capable of micron-scale gap formation, that allows the patterning of a larger variety of metals than the current portfolio of jettable metallic ink comprises and does not require a high-temperature sintering step. However, this method can produce large variations in gap size resulting in inconsistent and irreproducible transistor drain current. We propose that source-gated transistors (SGTs) are well suited to this technique, as they have a saturated drain current independent of source-drain separation, thus leading to improved current uniformity despite inconsistencies in gap size. © 2013 IEEE.

  • Cui Q, Si M, Sporea RA, Guo X. (2013) 'Simple noise margin model for optimal design of unipolar thin-film transistor logic circuits'. IEEE Transactions on Electron Devices, 60 (5), pp. 1782-1785.
  • Sporea RA, Shannon JM, Silva SRP. (2012) 'Modes of operation and optimum design for application of source-gated transistors'. ECS Transactions, 50 (8), pp. 65-70.
  • Sporea RA, Shannon JM, Silva SRP, Trainor MJ, Young ND. (2012) 'Field plate optimization in low-power high-gain source-gated transistors'. IEEE IEEE Transactions on Electron Devices, 59 (8), pp. 2180-2186.

    Abstract

    Source-gated transistors (SGTs) have potentially very high output impedance and low saturation voltages, which make them ideal as building blocks for high-performance analog circuits fabricated in thin-film technologies. The quality of saturation is greatly influenced by the design of the field-relief structure incorporated into the source electrode. Starting from measurements on self-aligned polysilicon structures, we show through numerical simulations how the field plate (FP) design can be improved. A simple source FP around 1 μm long situated several tens of nanometers above the semiconductor can increase the low-voltage intrinsic gain by more than two orders of magnitude and offers adequate tolerance to process variations in a moderately scaled thin-film SGT. © 2012 IEEE.

  • Sporea RA, Trainor MJ, Young ND, Shannon JM, Silva SRP. (2012) 'Field plate optimization in low-power high-gain source-gated transistors'. IEEE IEEE Transactions on Electron Devices, 59 (8)

    Abstract

    Source-gated transistors (SGTs) have potentially very high output impedance and low saturation voltages, which make them ideal as building blocks for high performance analog circuits fabricated in thin-film technologies. The quality of the saturation is greatly influenced by the design of the field-relief structure incorporated into the source electrode. Starting from measurements on self-aligned polysilicon structures, we show through numerical simulations how the field plate design can be improved. A simple source field plate around 1µm long situated several tens of nm above the semiconductor can increase the low-voltage intrinsic gain by more than two orders of magnitude and offers adequate tolerance to process variations in a moderately scaled thin-film SGT.

  • Sporea RA, Guo X, Shannon JM, Silva SRP. (2011) 'Source-Gated Transistors for Versatile Large Area Electronic Circuit Design and Fabrication'. Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors 3 Edition. The Electrochemical Society ECS Transactions, USA: 37 (1), pp. 57-63.

    Abstract

    Source-gated transistors (SGTs) comprise a blocking contact or potential barrier at the source, which control the current. The paper describes how SGTs can be optimized for particular applications and for specific semiconductor material systems. It is shown how the saturation voltage can be designed to be an order of magnitude smaller than in equivalent FETs to give power savings of over 50% for the same current output. The SGT also achieves a better saturation regime, with lower output conductance over a larger range of drain voltages. Flat-panel lighting, remote sensing and signal processing and large-area circuits made using inexpensive but imprecise patterning techniques are some of the applications which could benefit from incorporating these devices.

  • Sporea RA, Shannon JM, Silva SRP. (2011) 'High-resolution temperature sensing with source-gated transistors'. IEEE Device Research Conference (DRC), 2011 69th Annual, USA: , pp. 61-62.

    Abstract

    Source-gated transistors (SGTs) are three-terminal devices in which the current is controlled by a potential barrier at the source. The gate voltage is used primarily to modulate the effective height of the source barrier. These devices have a number of operational advantages over conventional field-effect transistors, including a potentially much smaller saturation voltage and very low output conductance in saturation, which lead to low power operation and high intrinsic gain.

  • Sporea RA, Trainor MJ, Young ND, Guo X, Shannon JM, Silva SRP. (2011) 'Performance trade-offs in polysilicon source-gated transistors'. Elsevier Solid-State Electronics, 65-66 (1), pp. 246-249.

    Abstract

    Self-aligned Schottky-source source-gated transistors (SGTs) have been made in polysilicon. The structures enable a direct comparison to be made between a SGT and a standard thin-film field-effect transistor (FET) on the same device. SGTs having excellent characteristics have been fabricated, with intrinsic gains approaching 10,000. The effects of bulk doping in the polysilicon and of the source barrier modification implant are considered in the context of the electrical output characteristics. It is shown that the choice of source length is a tradeoff between device speed and variations in current output due to variability during fabrication.

  • Sporea RA, Trainor MJ, Young ND, Guo X, Shannon JM, Silva SRP. (2011) 'Performance trade-offs in polysilicon source-gated transistors'. Solid-State Electronics, 65-66 (1), pp. 246-249.

    Abstract

    Self-aligned Schottky-source source-gated transistors (SGTs) have been made in polysilicon. The structures enable a direct comparison to be made between a SGT and a standard thin-film field-effect transistor (FET) on the same device. SGTs having excellent characteristics have been fabricated, with intrinsic gains approaching 10,000. The effects of bulk doping in the polysilicon and of the source barrier modification implant are considered in the context of the electrical output characteristics. It is shown that the choice of source length is a tradeoff between device speed and variations in current output due to variability during fabrication. © 2011 Elsevier Ltd. All rights reserved.

  • Sporea RA, Trainor MJ, Young ND, Shannon JM, Silva SRP. (2010) 'Intrinsic gain in self-aligned polysilicon source-gated transistors'. IEEE Transactions on Electron Devices, 57 (10), pp. 2434-2439.

    Abstract

    Thin-film, self-aligned source-gated transistors (SGTs) have been made in polysilicon. The very high output impedance of this type of transistor makes it suited to analog circuits. Intrinsic voltage gains of greater than one thousand have been measured at particular drain voltages. The drain voltage dependence of the gain is explained based on the device physics of the source-gated transistor and the fact that pinch-off occurs at both the source and the drain. The results obtained from these devices, which are far from optimal, suggest that, with proper design, the source-gated transistor is well suited to a wide range of analog applications.

  • Sporea RA, Guo X, Shannon JM, Silva SRP. (2010) 'Polysilicon source-gated transistors for mixed-signal systems-on-panel'. Electrochemical Society - 218th ECS Meeting Abstracts 2010, MA 2010-02, 3, pp. 1834-1834.
  • Sporea RA, Guo X, Shannon JM, Silva SRP. (2010) 'Polysilicon source-gated transistors for mixed-signal systems-on-panel'. Electrochemical Society ECS Transactions, 33 (5), pp. 419-424.

    Abstract

    The performance benefits of using source-gated transistors (SGTs) in analog large-area electronic circuits are examined practically and via numerical simulations. In current mirror circuits made using thin-film technology, significant advantages are observed for SGT implementations. A comparison of current mirrors implemented with standard field effect transistors (FETs) and SGTs shows that the SGT version can operate at a lower voltage and has larger output dynamic range for a given device geometry. The results are explained in relation to the saturation mechanisms of the SGT and are supported by experimental measurements of polysilicon devices.

  • Guo X, Sporea R, Shannon JM, Silva SRP. (2009) 'Down-scaling of thin-film transistors: Opportunities and design challenges'. ECS Transactions, 22 (1), pp. 227-238.

    Abstract

    With the ever-increasing demands for integration of advanced electronic functions into large-area electronics, down-scaling of thin-film transistors (TFTs) becomes very necessary. The key device operational issues associated with TFT scaling, including short-channel effects (SCEs) and self-heating, are considered in this paper. Device structure engineering approaches are introduced to suppress the SCEs for designing short-channel TFTs with excellent digital and analog performance. And electro-thermal simulation results show that the self-heating in TFTs will be much more significant than that in silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) due to the substrate of poor thermal conductivity. Enhancing the heat dissipation by placement of metal heat pipes in the cap dielectric layers is proved to be an effective way to deal with the heating issues. ©The Electrochemical Society.

  • Sporea DG, Sporea RA. (2005) 'Setup for the in situ monitoring of the irradiation-induced effects in optical fibers in the ultraviolet-visible optical range'. Review of Scientific Instruments, 76 (11), pp. 1-5.
  • Sporea DG, Sporea RA, Oproiu C, Vatǎ I. (2005) 'Comparative study of gamma-ray, neutron and electron beam irradiated index-guided laser diodes'. Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS,
  • Sporea DG, Oproiu C, Sporea RA. (2004) 'Degradation of heterojunction laser diodes under electron beam irradiation'. Proceedings of SPIE - The International Society for Optical Engineering, 5577 (PART 2), pp. 808-817.
  • Sporea DG, Sporea RA. (2003) 'Integrated software package for laser diodes characterization'. Proceedings of SPIE - The International Society for Optical Engineering, 5227, pp. 464-471.

Conference papers

  • Sporea RA, Georgakopoulos S, Xu X, Guo X, Shkunov M, Shannon JM, Silva SRP. (2013) 'Leveraging contact effects for field-effect transistor technologies with reduced complexity and superior current uniformity'. Materials Research Society Symposium Proceedings, 1553
  • Sporea RA, Shannon JM, Silva SRP, Guo X. (2011) 'Source-gated transistors for improved current-mode pixel drivers'. Kunshan, China: SID Asia Display / China Display 2011
  • Sporea RA, Shannon JM, Silva SRP, Trainor MJ, Young ND. (2010) 'Performance trade-offs in polysilicon source-gated transistors'. IEEE Proceedings of the European Solid State Device Research Conference, ESSDERC 2010, Sevilla, Spain: European Solid-State Device Research Conference (ESSDERC), pp. 222-225.

    Abstract

    Self-aligned Schottky-source source-gated transistors (SGTs) have been made in polysilicon. The structures enable a direct comparison to be made between a SGT and a standard thin-film field-effect transistor (FET) on the same device. SGTs having excellent characteristics have been fabricated, with intrinsic gains approaching 10,000. The effects of bulk doping in the polysilicon and of the source barrier modification implant are considered in the context of the electrical output characteristics. It is shown that the choice of source length is a tradeoff between device speed and current uniformity.

  • Sporea RA, Trainor MJ, Young ND, Shannon JM, Silva SRP. (2010) 'Performance improvements in polysilicon source-gated transistors'. IEEE DRC Conference Digest, Indiana, USA: 68th Device Research Conference, pp. 245-246.

    Abstract

    The source-gated transistor (SGT) is a new type of transistor in which the current is controlled by a potential barrier at the source and by a gate which modulates the effective height of the source barrier. It is an ideal device architecture to be used with the low mobility materials typically applied to large area electronics, as it provides low saturation voltages and high output impedances. Furthermore, the high internal fields and low concentration of excess carriers lead to higher speed and better stability compared with FETs, particularly in disordered, low mobility semiconductors. As such, the SGT is especially well suited to thin-film analog circuits.

  • Sporea RA, Shannon JM, Silva SRP. (2010) 'Properties of source-gated transistors in polysilicon'. IEEE 6th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2010, Berlin, Germany: PRIME 2010

    Abstract

    This paper describes some of the performance characteristics of self-aligned polysilicon Schottky Source- Gated Transistors (SGTs) made on glass by laser annealing of amorphous silicon. The threshold and Schottky barrier height are tuned by varying the dose of dopants in the bulk and under the source respectively. These devices are well suited for analog applications owing to their low saturation voltage, low drain field dependence of the current and intrinsic gain which is in excess of 1000 for well designed structures. Double drain operation leads to fT ≈100MHz for non-optimized devices. Index Terms— Source-Gated Transistor, polysilicon, analog

  • Sporea RA, Guo X, Shannon JM, Silva SRP. (2009) 'Effects of process variations on the current in Schottky Barrier Source-Gated Transistors'. IEEE Proceedings of the International Semiconductor Conference (CAS), Sinaia, Romania: CAS 2009 2, pp. 413-416.

    Abstract

    The sensitivity of the drain current in Schottky barrier source-gated transistors to process variation is studied using computer simulations. It is shown that provided the device is designed correctly, the current is independent of source-drain separation and is insensitive to source length variations. However, uniform insulator thickness and precise control of the source barrier is needed if good current uniformity is to be obtained.

Other publications

  • Sporea RA, Trainor M, Young N, Shannon JM, Silva SRP. (2015) Temperature Effects in Complementary Inverters Made With Polysilicon Source-Gated Transistors. Electron Devices, IEEE Transactions on, PP (99), pp. 1-1.

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