My research project

My qualifications

BEng Electronic Engineering with Nanotechnology
University of Surrey
MSc Cognitive and Clinical Neuroscience
University of London

Affiliations and memberships

IEEE Electron Devices Society
Student member
Student member


Research interests

My teaching

My publications


Eva Bestelink, Kham Niang, Georgios Bairaktaris, Luca Maiolo, Francesco Maita, Kalil Ali, Andrew J. Flewitt, S. Ravi P. Silva, and Radu A. Sporea (2020). Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors
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Silicon-based digital electronics have evolved over decades through an aggressive scaling process following Moore’s law with increasingly complex device structures. Simultaneously, large-area electronics have continued to rely on the same field-effect transistor structure with minimal evolution. This limitation has resulted in less than ideal circuit designs, with increased complexity to account for shortcomings in material properties and process control. At present, this situation is holding back the development of novel systems required for printed and flexible electronic applications beyond the Internet of Things. In this work we demonstrate the opportunity offered by the source-gated transistor’s unique properties for low-cost, highly functional large-area applications in two extremely compact circuit blocks. Polysilicon common-source amplifiers show 49 dB gain, the highest reported for a twotransistor unipolar circuit. Current mirrors fabricated in polysilicon and InGaZnO have, in addition to excellent current copying performance, the ability to control the temperature dependence (degrees of positive, neutral or negative) of output current solely by choice of relative transistor geometry, giving further flexibility to the design engineer. Application examples are proposed, including local amplification of sensor output for improved signal integrity, as well as temperature-regulated delay stages and timing circuits for homeostatic operation in future wearables. Numerous applications will benefit from these highly competitive compact circuit designs with robust performance, improved energy efficiency and tolerance to geometrical variations: sensor front-ends, temperature sensors, pixel drivers, bias analog blocks and high-gain amplifiers.
Eva Bestelink, S. Ravi P. Silva, Radu A. Sporea, Luca Maiolo, Francesco Maita (2019). 49dB depletion-load amplifiers with polysilicon source-gated transistors
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Two-transistor zero-VGS amplifiers made with polysilicon source-gated transistors achieve voltage gain approaching 300 (49dB). TCAD simulations reveal the effect of load and driver transistor geometry on gain and operating frequency. The SGT circuits have simultaneously superior gain and reduced layout area (two-transistor, channel length L = 3μm and width W = 10 and 30μm), relative to conventional TFT implementations. These results recommend low-complexity, compact SGT designs for flexible and printed amplifiers, such as bio- and chemical sensors.
Raymond Drury, Eva Bestelink, Radu A. Sporea (2019). Simulation Study of Overlap Capacitance in Source-Gated Transistors for Current-Mode Pixel Drivers
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Contrary to conventional design principles, current-driven pixel drivers based on source-gated transistors (SGTs) achieve their optimal drive current and speed with a deliberate 5-10-μm gate-source overlap. Total pixel circuit area need not increase, as the additional device area can be compensated by reducing the pixel storage capacitor. The numerical simulations demonstrate the viability of SGTs for emissive pixel drivers and high gain, low power, and robust circuits for emerging sensor arrays.
Eva Bestelink, Thoran Landers and Radu A. Sporea (2019). Turn-off mechanisms in thin-film source-gated transistors with applications to power devices and rectification
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We describe the physics of the turn-off mechanism in source-gated transistors (SGTs), which is distinct from that of conventional thin-film field-effect transistors and allows significantly lower off currents, particularly in depletion-mode devices. The “n-type” SGT enters its off state when the potential applied across the semiconductor layer is decreased to low positive values or made negative through the applied gate bias, thus impeding charge injection from the source contact. Measurements on polysilicon devices were supported with TCAD simulations using Silvaco Atlas. Alongside the other known benefits of SGTs, including low saturation voltage, tolerance to process variations, and high intrinsic gain, the ability to efficiently block current at high negative gate voltages suggests that these devices would be ideal elements in emerging thin-film power management and rectification circuits.
Eva Bestelink Olivier de Sagazan, Max Bateson and Radu A. Sporea (2020). 31‐1: Invited Paper: The Multimodal Thin‐Film Transistor (MMT): A Versatile Low‐Power and High‐Gain Device with Inherent Linear Response
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A new device, the Multimodal Transistor (MMT), separates charge injection from conduction. With design optimization, it can achieve a constant transconductance with independent on/off switching of output current. This functionality has ample applications in energy efficient analog computation and hardware learning.
Eva Bestelink, Olivier de Sagazan and Radu A. Sporea (2020). P‐18: Ultra‐Compact Multi‐Level Digital‐to‐Analog Converter based on Linear Multimodal Thin‐Film Transistors
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A new device, the Multimodal Transistor (MMT), separates charge injection from conduction and achieves a linear dependence of drain current on its control gate voltage. This functionality is used to implement a highly compact digital‐to‐analog‐converter, capable of performing 3‐level, 3‐bit conversion with minimal error (1.2% of LSB).
Olivier de Sagazan, Andreï Uvarov, Eva Bestelink, Radu A. Sporea and Emmanuel Jacques (2020). P‐51: Investigation on ICP‐CVD as a Polyvalent Low Cost Technology Dedicated to Low Temperature μ‐Si TFT Prototyping
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A Corial Inductively Coupled Plasma Chemical Vapor Deposition (ICP‐CVD) system has been investigated to produce un‐doped and doped μ‐Si layers, as well as insulators, leading to a general capability of performing N and P type TFTs. This enables to develop rapid prototyping of TFTs. Resistivity of layers and TFT issues from ICP‐CVD have been electrically characterized.
Eva Bestelink, André Dale and Radu A. Sporea (2020). P‐195: Late‐News‐Poster: Data Retention in Pixel Drivers Based on Source‐Gated Transistors
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We have recently demonstrated that, contrary to conventional TFT design rules, emissive pixels based on source‐gated transistor drivers benefit from choosing a source‐gate overlap of several microns. Using TCAD simulations we show that incorporating the SGT overlap capacitance with that of the conventional storage capacitor, pixel area can be optimized, with no adverse impact on data retention. For the technology considered, the optimum source‐gate overlap was 4 ‐ 8 μm, which is in the range of highest operating frequencies for source‐gated transistors.