My research project

My qualifications

2018
BEng Electronic Engineering with Nanotechnology
University of Surrey
2014
MSc Cognitive and Clinical Neuroscience
University of London

Affiliations and memberships

IEEE Electron Devices Society
Student member
IET
Student member
SID
Student member
ECS
Student member

Research

Research interests

My teaching

My publications

Publications

E. Bestelink, O. de Sagazan, L. Motte, M. Bateson, B. Schultes, S. R. P. Silva, R. A. Sporea (2020). Versatile Thin‐Film Transistor with Independent Control of Charge Injection and Transport for Mixed Signal and Analog Computation
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New materials and optimized fabrication techniques have led to steady evolution in large area electronics, yet significant advances come only with new approaches to fundamental device design. The multimodal thin‐film transistor introduced here offers broad functionality resulting from separate control of charge injection and transport, essentially using distinct regions of the active material layer for two complementary device functions, and is material agnostic. The initial implementation uses mature processes to focus on the device's fundamental benefits. A tenfold increase in switching speed, linear input–output dependence, and tolerance to process variations enable low‐distortion amplifiers and signal converters with reduced complexity. Floating gate designs eliminate deleterious drain voltage coupling for superior analog memory or computing. This versatile device introduces major new opportunities for thin‐film technologies, including compact circuits for integrated processing at the edge and energy‐efficient analog computation.
E. Bestelink, O. de Sagazan, R. A. Sporea (2020). Total Gain Recovery in Floating Gate Thin-Film Transistors for Neuromorphic and Edge Computing
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We propose a floating-gate (FG) thin-film transistor architecture which alleviates a significant limitation present since the inception of FG field-effect transistors, namely the loss of gain due to parasitic capacitive coupling on the FG [1]. The interest in large area electronics has grown beyond traditional applications, such as display and sensing arrays, with recent trends including neuromorphic and edge computing. However, the challenges of fabricating robust thin film transistor (TFT) circuits have remained despite the many significant achievements in material systems and process development. In order to realise the full benefit of low-cost, high-throughput manufacturing methods, device shortcomings need to be addressed [2]. In FG devices, specifically, one major limitation is the degradation of gain compared to conventional devices, as a result of capacitive coupling of the channel and drain potentials to the floating gate. The problem is far more severe in contact-controlled TFTs, such as the staggered-electrode, high-gain source-gated transistor (SGT) [3, 4], and crippling in conventional TFTs manufactured in materials such as InGaZnO [5]. SGT operation differs from conventional field-effect TFTs, whereby the semiconductor is fully depleted at the source edge by an energy barrier (e.g. Schottky), which is reverse biased by the application of drain voltage. Charge injection is modulated via the gate/source overlap, producing very low saturation voltage and ultra-low output conductance [3]. This latter feature yields the distinctive and extremely high intrinsic gain observed in such devices. A large voltage drop occurs across the source depletion region, producing the notable early saturation and, consequently, the channel potential is maintained at a value close to the drain potential for operating conditions in which a conventional TFT would still be working in the linear region. As such, when a floating gate is used in a SGT, the FG couples strongly to both the drain and the channel. FG potential varies considerably with drain voltage, thus increasing charge injection along the source, ultimately raising . While is still orders of magnitude lower than that of a TFT or FG TFT (see Figure 1), many analog applications would benefit from a solution to this problem [1]. Here, we present a staggered-electrode contact-controlled device, the multimodal transistor (MMT), which shares SGT charge injection principles, however the switching mechanism of its channel is controlled by a separate gate [6]. In a FG MMT, the source gate responsible for charge injection and channel switching gate are designed as FGs (FG1 and FG2, respectively) and a main control gate (CG) may overlap both FGs. FG MMTs have been fabricated in low T°C technology [6] with Ni source and drain contacts. ICP-CVD (Inductively Coupled Plasma Chemical Vapour Deposition) via the Corial 210D reactor was used to deposit µ-Si as active layer, as well as the insulators of the gate stack (Figure 1a). Temperature never exceeded 250°C in any of the processing steps. The MMT exhibits the same high-gain properties of the SGT and preserves it even in FG configuration. With the channel and drain potentials coupling to FG2, its potential is raised significantly higher than FG1 (see Figures 1b and 1c for TCAD simulation with Silvaco Atlas), which is effectively shielded. As charge injection is exclusively modulated by FG1, the low saturation and extremely low are maintained, in contrast to the FG SGT (see Figure 1c). Thus, extremely high gain can be obtained from the FG MMT structure, with a wide range of applicability to traditional analog applications such as displays and sensors, as well as emerging neuromorphic circuits.
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Eva Bestelink, Kham Niang, Georgios Bairaktaris, Luca Maiolo, Francesco Maita, Kalil Ali, Andrew J. Flewitt, S. Ravi P. Silva, and Radu A. Sporea (2020). Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors
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Silicon-based digital electronics have evolved over decades through an aggressive scaling process following Moore’s law with increasingly complex device structures. Simultaneously, large-area electronics have continued to rely on the same field-effect transistor structure with minimal evolution. This limitation has resulted in less than ideal circuit designs, with increased complexity to account for shortcomings in material properties and process control. At present, this situation is holding back the development of novel systems required for printed and flexible electronic applications beyond the Internet of Things. In this work we demonstrate the opportunity offered by the source-gated transistor’s unique properties for low-cost, highly functional large-area applications in two extremely compact circuit blocks. Polysilicon common-source amplifiers show 49 dB gain, the highest reported for a twotransistor unipolar circuit. Current mirrors fabricated in polysilicon and InGaZnO have, in addition to excellent current copying performance, the ability to control the temperature dependence (degrees of positive, neutral or negative) of output current solely by choice of relative transistor geometry, giving further flexibility to the design engineer. Application examples are proposed, including local amplification of sensor output for improved signal integrity, as well as temperature-regulated delay stages and timing circuits for homeostatic operation in future wearables. Numerous applications will benefit from these highly competitive compact circuit designs with robust performance, improved energy efficiency and tolerance to geometrical variations: sensor front-ends, temperature sensors, pixel drivers, bias analog blocks and high-gain amplifiers.
Eva Bestelink, S. Ravi P. Silva, Radu A. Sporea, Luca Maiolo, Francesco Maita (2019). 49dB depletion-load amplifiers with polysilicon source-gated transistors
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Two-transistor zero-VGS amplifiers made with polysilicon source-gated transistors achieve voltage gain approaching 300 (49dB). TCAD simulations reveal the effect of load and driver transistor geometry on gain and operating frequency. The SGT circuits have simultaneously superior gain and reduced layout area (two-transistor, channel length L = 3μm and width W = 10 and 30μm), relative to conventional TFT implementations. These results recommend low-complexity, compact SGT designs for flexible and printed amplifiers, such as bio- and chemical sensors.
Raymond Drury, Eva Bestelink, Radu A. Sporea (2019). Simulation Study of Overlap Capacitance in Source-Gated Transistors for Current-Mode Pixel Drivers
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Contrary to conventional design principles, current-driven pixel drivers based on source-gated transistors (SGTs) achieve their optimal drive current and speed with a deliberate 5-10-μm gate-source overlap. Total pixel circuit area need not increase, as the additional device area can be compensated by reducing the pixel storage capacitor. The numerical simulations demonstrate the viability of SGTs for emissive pixel drivers and high gain, low power, and robust circuits for emerging sensor arrays.
Eva Bestelink, Thoran Landers and Radu A. Sporea (2019). Turn-off mechanisms in thin-film source-gated transistors with applications to power devices and rectification
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We describe the physics of the turn-off mechanism in source-gated transistors (SGTs), which is distinct from that of conventional thin-film field-effect transistors and allows significantly lower off currents, particularly in depletion-mode devices. The “n-type” SGT enters its off state when the potential applied across the semiconductor layer is decreased to low positive values or made negative through the applied gate bias, thus impeding charge injection from the source contact. Measurements on polysilicon devices were supported with TCAD simulations using Silvaco Atlas. Alongside the other known benefits of SGTs, including low saturation voltage, tolerance to process variations, and high intrinsic gain, the ability to efficiently block current at high negative gate voltages suggests that these devices would be ideal elements in emerging thin-film power management and rectification circuits.
Eva Bestelink Olivier de Sagazan, Max Bateson and Radu A. Sporea (2020). 31‐1: Invited Paper: The Multimodal Thin‐Film Transistor (MMT): A Versatile Low‐Power and High‐Gain Device with Inherent Linear Response
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A new device, the Multimodal Transistor (MMT), separates charge injection from conduction. With design optimization, it can achieve a constant transconductance with independent on/off switching of output current. This functionality has ample applications in energy efficient analog computation and hardware learning.
Eva Bestelink, Olivier de Sagazan and Radu A. Sporea (2020). P‐18: Ultra‐Compact Multi‐Level Digital‐to‐Analog Converter based on Linear Multimodal Thin‐Film Transistors
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A new device, the Multimodal Transistor (MMT), separates charge injection from conduction and achieves a linear dependence of drain current on its control gate voltage. This functionality is used to implement a highly compact digital‐to‐analog‐converter, capable of performing 3‐level, 3‐bit conversion with minimal error (1.2% of LSB).
Olivier de Sagazan, Andreï Uvarov, Eva Bestelink, Radu A. Sporea and Emmanuel Jacques (2020). P‐51: Investigation on ICP‐CVD as a Polyvalent Low Cost Technology Dedicated to Low Temperature μ‐Si TFT Prototyping
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A Corial Inductively Coupled Plasma Chemical Vapor Deposition (ICP‐CVD) system has been investigated to produce un‐doped and doped μ‐Si layers, as well as insulators, leading to a general capability of performing N and P type TFTs. This enables to develop rapid prototyping of TFTs. Resistivity of layers and TFT issues from ICP‐CVD have been electrically characterized.
Eva Bestelink, André Dale and Radu A. Sporea (2020). P‐195: Late‐News‐Poster: Data Retention in Pixel Drivers Based on Source‐Gated Transistors
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We have recently demonstrated that, contrary to conventional TFT design rules, emissive pixels based on source‐gated transistor drivers benefit from choosing a source‐gate overlap of several microns. Using TCAD simulations we show that incorporating the SGT overlap capacitance with that of the conventional storage capacitor, pixel area can be optimized, with no adverse impact on data retention. For the technology considered, the optimum source‐gate overlap was 4 ‐ 8 μm, which is in the range of highest operating frequencies for source‐gated transistors.