Dr Radu Sporea


Lecturer in Semiconductor Devices
+44 (0)1483 686086
28 ATI 02

Biography

Areas of specialism

Electronic devices and circuits; Flexible and printed electronics; Manufacturability and reliability of electronics; Modelling and simulation; Unconventional electronics

Business, industry and community links

Research

Research interests

My teaching

Supervision

Postgraduate research supervision

My publications

Publications

Sporea RA, Guo X, Shannon JM, Silva SRP (2010) Polysilicon source-gated transistors for mixed-signal systems-on-panel, ECS Transactions 33 (5) pp. 419-424 Electrochemical Society
The performance benefits of using source-gated transistors (SGTs)
in analog large-area electronic circuits are examined practically
and via numerical simulations. In current mirror circuits made
using thin-film technology, significant advantages are observed for
SGT implementations. A comparison of current mirrors
implemented with standard field effect transistors (FETs) and
SGTs shows that the SGT version can operate at a lower voltage
and has larger output dynamic range for a given device geometry.
The results are explained in relation to the saturation mechanisms
of the SGT and are supported by experimental measurements of
polysilicon devices.
Sporea DG, Sporea RA, Oproiu C, VatÎ I (2005) Comparative study of gamma-ray, neutron and electron beam irradiated index-guided laser diodes, Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS
The effect of gamma-ray, neutron and electron beam irradiation on index-guided laser diodes was investigated off-line. The laser diodes subjected to this evaluation were AlGaAs, low power (8 mW), single transversal mode lasers emitting in the near-IR. The diodes degradation was assessed up to the total gamma dose of 1.23 MGy, the total electron beam dose of 0.6 MGy, and to the neutron fluence of 1.2 × 1013 n/cm2. The electrical, optical and optoelectronic characteristics were studied. The major irradiation induced changes are related to the embedded photodiode responsivity, the laser threshold current and its external quantum efficiency.
Sporea RA, Shannon JM, Silva SRP (2010) Properties of source-gated transistors in polysilicon, 6th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2010 IEEE
This paper describes some of the performance
characteristics of self-aligned polysilicon Schottky Source-
Gated Transistors (SGTs) made on glass by laser annealing of
amorphous silicon. The threshold and Schottky barrier height
are tuned by varying the dose of dopants in the bulk and under
the source respectively. These devices are well suited for analog
applications owing to their low saturation voltage, low drain
field dependence of the current and intrinsic gain which is in
excess of 1000 for well designed structures. Double drain
operation leads to fT H100MHz for non-optimized devices.
Index Terms? Source-Gated Transistor, polysilicon, analog
Sporea RA, Shannon JM, Silva SRP, Trainor MJ, Young ND (2012) Field plate optimization in low-power high-gain source-gated transistors, IEEE Transactions on Electron Devices 59 (8) pp. 2180-2186 IEEE
Source-gated transistors (SGTs) have potentially very high output impedance and low saturation voltages, which make them ideal as building blocks for high-performance analog circuits fabricated in thin-film technologies. The quality of saturation is greatly influenced by the design of the field-relief structure incorporated into the source electrode. Starting from measurements on self-aligned polysilicon structures, we show through numerical simulations how the field plate (FP) design can be improved. A simple source FP around 1 ¼m long situated several tens of nanometers above the semiconductor can increase the low-voltage intrinsic gain by more than two orders of magnitude and offers adequate tolerance to process variations in a moderately scaled thin-film SGT. © 2012 IEEE.
Sporea RA, Georgakopoulos S, Shkunov M, Shannon JM, Silva SRP, Xu X, Guo X (2013) Leveraging contact effects for field-effect transistor technologies with reduced complexity and superior current uniformity, MRS Online Proceedings Library 1553
In order to achieve high performance, the design of devices for large-area electronics needs to be optimized despite material or fabrication shortcomings. In numerous emerging technologies thin-film transistor (TFT) performance is hindered by contact effects. Here, we show that contact effects can be used constructively to create devices with performance characteristics unachievable by conventional transistor designs. Source-gated transistors (SGTs) are not designed with increasing transistor speed, mobility or sub-threshold slope in mind, but rather with improving certain aspects critical for real-world large area electronics such as stability, uniformity, power efficiency and gain. SGTs can achieve considerably lower saturation voltage and power dissipation compared to conventional devices driven at the same current; higher output impedance for over two orders of magnitude higher intrinsic gain; improved bias stress stability in amorphous materials; higher resilience to processing variations; current virtually independent of source-drain gap, source-gate overlap and semiconductor thickness variations. Applications such as amplifiers and drivers for sensors and actuators, low cost large area analog or digital circuits could greatly benefit from incorporating the SGT architecture.
Dahiya AS, Opoku C, Sporea RA, Sarvankumar B, Poulin-Vittrant G, Cayrel F, Camara N, Alquier D (2016) Single-crystalline ZnO sheet Source-Gated Transistors, Scientific Reports 6 19232 Nature Publishing Group
Due to their fabrication simplicity, fully compatible with low-cost large-area device assembly strategies, source-gated transistors (SGTs) have received significant research attention in the area of high-performance electronics over large area low-cost substrates. While usually based on either amorphous or polycrystalline silicon (±-Si and poly-Si, respectively) thin-film technologies, the present work demonstrate the assembly of SGTs based on single-crystalline ZnO sheet (ZS) with asymmetric ohmic drain and Schottky source contacts. Electrical transport studies of the fabricated devices show excellent field-effect transport behaviour with abrupt drain current saturation (IDSSAT) at low drain voltages well below 2 V, even at very large gate voltages. The performance of a ZS based SGT is compared with a similar device with ohmic source contacts. The ZS SGT is found to exhibit much higher intrinsic gain, comparable on/off ratio and low off currents in the sub-picoamp range. This approach of device assembly may form the technological basis for highly efficient low-power analog and digital electronics using ZnO and/or other semiconducting nanomaterial.
Shannon JM, Sporea RA, Georgakopoulos S, Shkunov M, Silva SRP (2013) Low-Field Behavior of Source-Gated Transistors, IEEE Transactions on Electron Devices 60 (8) pp. 2444-2449 IEEE
A physical description of low-field behavior of a Schottky source-gated transistor (SGT) is outlined where carriers crossing the source barrier by thermionic emission are restricted by JFET action in the pinch-off region at the drain end of the source. This mode of operation leads to transistor characteristics with low saturation voltage and high output impedance without the need for field relief at the edge of the Schottky source barrier and explains many characteristics of SGT observed experimentally. 2-D device simulations with and without barrier lowering due to the Schottky effect show that the transistors can be designed so that the current is independent of source length and thickness variations in the semiconductor. This feature together with the fact that the current in an SGT is independent of source-drain separation hypothesizes the fabrication of uniform current sources and other large-area analog circuit blocks with repeatable performance even in imprecise technologies such as high-speed printing.
Sporea DG, Oproiu C, Sporea RA (2004) Degradation of heterojunction laser diodes under electron beam irradiation, Proceedings of SPIE - The International Society for Optical Engineering 5577 (PART 2) pp. 808-817
We are reporting the investigation on the degradation of heterojunction laser diodes as they were subjected to electron beam irradiation. The research was done under the European Union's Fusion Programme, and targets the possible use of semiconductor lasers for remote sensing and robotics, under irradiation conditions. A total irradiation dose of 600 kGy was achieved at room temperature. The measurements were performed off-line using an automatic measuring set-up. Following each irradiation step, several characteristics of the laser diodes were monitored, as function of the driving current and the case temperature: the emitted optical power, the wavelength of the emitted radiation, the embedded photodiode current, the longitudinal and transversal mode structure, as well as the temporal behavior of all these parameters. For each irradiation dose, the laser diode serial resistance, threshold current, and quantum efficiency, and the photodiode responsivity were plotted for different operating conditions.
Sporea RA, Lygo-Baker S (2016) Summer Research Placements - State-of-the-Art Science by pre-University Students, MRS Advances MRSF15-2327286.R1
Summer research placements are an effective training and research tool. Over three years, our group has hosted nine pre-university students over periods of four to six weeks. Apart from student training and skills acquisition, the placements have produced several peer-reviewed technical publications. Our approach relies on careful pre-planning of activities, frequent student interaction, coupled with independent and group learning. We explore the advantages and disadvantages of this manner of running summer placements.
Sporea RA, Trainor MJ, Young ND, Shannon JM, Silva SRP (2012) Field plate optimization in low-power high-gain source-gated transistors, IEEE Transactions on Electron Devices 59 (8) IEEE
Source-gated transistors (SGTs) have potentially very high output impedance and low saturation voltages, which make them ideal as building blocks for high performance analog circuits fabricated in thin-film technologies. The quality of the saturation is greatly influenced by the design of the field-relief structure incorporated into the source electrode. Starting from measurements on self-aligned polysilicon structures, we show through numerical simulations how the field plate design can be improved. A simple source field plate around 1µm long situated several tens of nm above the semiconductor can increase the low-voltage intrinsic gain by more than two orders of magnitude and offers adequate tolerance to process variations in a moderately scaled thin-film SGT.
Sporea RA, Shannon JM, Silva SRP, Trainor MJ, Young ND (2010) Performance trade-offs in polysilicon source-gated transistors, Proceedings of the European Solid State Device Research Conference, ESSDERC 2010 pp. 222-225 IEEE
Self-aligned Schottky-source source-gated transistors (SGTs) have been made in polysilicon. The structures enable a direct comparison to be made between a SGT and a standard thin-film field-effect transistor (FET) on the same device. SGTs having excellent characteristics have been fabricated, with intrinsic gains approaching 10,000. The effects of bulk doping in the polysilicon and of the source barrier modification implant are considered in the context of the electrical output characteristics. It is shown that the choice of source length is a tradeoff between device speed and current uniformity.
Sporea RA, Burridge T, Silva SRP (2015) Self-Heating Effects In Polysilicon Source Gated Transistors, SCIENTIFIC REPORTS 5 ARTN 14058 NATURE PUBLISHING GROUP
Sporea RA, Trainor M, Young N, Shannon JM, Silva SRP (2015) Temperature Effects in Complementary Inverters Made With Polysilicon Source-Gated Transistors, Electron Devices, IEEE Transactions on PP (99) pp. 1-1
Through their high gain and low saturation voltage, source-gated transistors (SGTs) have applications in both analog and digital thin-film circuits. In this paper, we show how we can design SGT-based logic gates, which are practically unaffected by temperature variations. We discuss design characteristics, which ensure reliable operation in spite of SGT temperature dependence of drain current, and their implications for manufacturability and large signal operation.
Sporea RA, Trainor MJ, Young ND, Guo X, Shannon JM, Silva SRP (2011) Performance trade-offs in polysilicon source-gated transistors, Solid-State Electronics 65-66 (1) pp. 246-249 Elsevier
Self-aligned Schottky-source source-gated transistors (SGTs) have been
made in polysilicon. The structures enable a direct comparison to be made between
a SGT and a standard thin-film field-effect transistor (FET) on the same device.
SGTs having excellent characteristics have been fabricated, with intrinsic gains
approaching 10,000. The effects of bulk doping in the polysilicon and of the source
barrier modification implant are considered in the context of the electrical output
characteristics. It is shown that the choice of source length is a tradeoff between
device speed and variations in current output due to variability during fabrication.
Guo X, Sporea R, Shannon JM, Silva SRP (2009) Down-scaling of thin-film transistors: Opportunities and design challenges, ECS Transactions 22 (1) pp. 227-238
With the ever-increasing demands for integration of advanced electronic functions into large-area electronics, down-scaling of thin-film transistors (TFTs) becomes very necessary. The key device operational issues associated with TFT scaling, including short-channel effects (SCEs) and self-heating, are considered in this paper. Device structure engineering approaches are introduced to suppress the SCEs for designing short-channel TFTs with excellent digital and analog performance. And electro-thermal simulation results show that the self-heating in TFTs will be much more significant than that in silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) due to the substrate of poor thermal conductivity. Enhancing the heat dissipation by placement of metal heat pipes in the cap dielectric layers is proved to be an effective way to deal with the heating issues. ©The Electrochemical Society.
Cui Q, Si M, Sporea RA, Guo X (2013) Simple noise margin model for optimal design of unipolar thin-film transistor logic circuits, IEEE Transactions on Electron Devices 60 (5) pp. 1782-1785
The noise margin (NM) of an inverter is an important feature for the operation stability of the digital circuits. Owing to their simple structure, easy processes, and relatively high gain, the unipolar zero-VGS-load logic design is widely used for implementation of digital circuits in various thin-film transistor (TFT) technologies. In this paper, a simple NM model clarifying the relationship between the NM and electrical/device parameters is developed for the zero-VGS-load inverter. The model is verified by circuit simulations, and is capable of providing a useful guideline for optimal design of unipolar TFT logic circuits. Finally, the application of the derived model in a static random access memory cell design is discussed. © 2013 IEEE.
Sporea RA, Trainor MJ, Young ND, Shannon JM, Silva SR (2014) Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits., Sci Rep 4
Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.
Sporea RA, Wright W, Shannon JM, Silva SRP (2015) Bulk barrier source-gated transistors with improved drain current dynamic range and temperature coefficient, ECS Transactions 67 (1) pp. 91-96
© The Electrochemical Society.Source-gated thin-film transistors (SGTs) have remarkable properties related to low-voltage amplification, tolerance to process variation and electrical stability. They rely on a potential barrier at the source in their operation, and usually this barrier is realized through a Schottky contact. Here, we study SGTs with source barriers made by doping the source region of the semiconductor to form bulk unipolar diodes (BUD). A BUSGT can have much higher drain current with a lower activation energy, resulting in higher switching speed and improved transconductance. Barriers made via doping also provide a wider range of barrier heights compared with Schottky contacts. We discuss design parameters for BUSGTs and compare these devices with SBSGTs.
Sporea RA, Trainor MJ, Young ND, Shannon JM, Silva SRP (2010) Intrinsic gain in self-aligned polysilicon source-gated transistors, IEEE Transactions on Electron Devices 57 (10) pp. 2434-2439
Thin-film, self-aligned source-gated transistors (SGTs) have been made in polysilicon.
The very high output impedance of this type of transistor makes it suited to analog circuits.
Intrinsic voltage gains of greater than one thousand have been measured at particular drain
voltages. The drain voltage dependence of the gain is explained based on the device physics
of the source-gated transistor and the fact that pinch-off occurs at both the source and the
drain. The results obtained from these devices, which are far from optimal, suggest that, with
proper design, the source-gated transistor is well suited to a wide range of analog applications.
Sporea RA, Shannon JM, Silva SRP, Guo X (2011) Source-gated transistors for improved current-mode pixel drivers,
Emissive displays require high-efficiency linear drivers which are stable under electrical stress and can deliver uniform performance across a large area. Owing to their low saturation voltage and flat saturation characteristic, source-gated transistors (SGTs) are ideally suited to act as power-efficient driving transistors in active matrix backplanes for lighting, low-power signage and display screens. It is shown that SGTs are also very stable during electrical stress. The technology is compatible with standard TFT fabrication allowing FET and SGT devices to be integrated in the same design and fabrication run.
Sporea RA, Trainor MJ, Young ND, Shannon JM, Silva SRP (2010) Performance improvements in polysilicon source-gated transistors, DRC Conference Digest pp. 245-246 IEEE
The source-gated transistor (SGT) is a new type of transistor in which the current is controlled by a potential barrier at the source and by a gate which modulates the effective height of the source barrier. It is an ideal device architecture to be used with the low mobility materials typically applied to large area electronics, as it provides low saturation voltages and high output impedances. Furthermore, the high internal fields and low concentration of excess carriers lead to higher speed and better stability compared with FETs, particularly in disordered, low mobility semiconductors. As such, the SGT is especially well suited to thin-film analog circuits.
Sporea RA, Guo X, Shannon JM, Silva SRP (2011) Source-Gated Transistors for Versatile Large Area Electronic Circuit Design and Fabrication, ECS Transactions 37 (1) pp. 57-63 The Electrochemical Society
Source-gated transistors (SGTs) comprise a blocking contact or potential barrier at the source, which control the current. The paper describes how SGTs can be optimized for particular applications and for specific semiconductor material systems. It is shown how the saturation voltage can be designed to be an order of magnitude smaller than in equivalent FETs to give power savings of over 50% for the same current output. The SGT also achieves a better saturation regime, with lower output conductance over a larger range of drain voltages. Flat-panel lighting, remote sensing and signal processing and large-area circuits made using inexpensive but imprecise patterning techniques are some of the applications which could benefit from incorporating these devices.
Sporea RA, Georgakopoulos S, Shkunov M, Shannon JM, Silva SRP, Xu X, Guo X (2013) Leveraging contact effects for field-effect transistor technologies with reduced complexity and superior current uniformity, International Review of the Red Cross 1553 (888)
In order to achieve high performance, the design of devices for large-area electronics needs to be optimized despite material or fabrication shortcomings. In numerous emerging technologies thin-film transistor (TFT) performance is hindered by contact effects. Here, we show that contact effects can be used constructively to create devices with performance characteristics unachievable by conventional transistor designs. Source-gated transistors (SGTs) are not designed with increasing transistor speed, mobility or sub-threshold slope in mind, but rather with improving certain aspects critical for real-world large area electronics such as stability, uniformity, power efficiency and gain. SGTs can achieve considerably lower saturation voltage and power dissipation compared to conventional devices driven at the same current; higher output impedance for over two orders of magnitude higher intrinsic gain; improved bias stress stability in amorphous materials; higher resilience to processing variations; current virtually independent of source-drain gap, source-gate overlap and semiconductor thickness variations. Applications such as amplifiers and drivers for sensors and actuators, low cost large area analog or digital circuits could greatly benefit from incorporating the SGT architecture.
Sporea RA, Alshammari AS, Georgakopoulos S, Underwood J, Shkunov M, Silva SRP (2013) Micron-scale inkjet-assisted digital lithography for large-area flexible electronics, European Solid-State Device Research Conference pp. 280-283
Large-area electronics require cost-effective yet precise patterning of electrodes. We demonstrate a simple electrode patterning technique capable of micron-scale gap formation, that allows the patterning of a larger variety of metals than the current portfolio of jettable metallic ink comprises and does not require a high-temperature sintering step. However, this method can produce large variations in gap size resulting in inconsistent and irreproducible transistor drain current. We propose that source-gated transistors (SGTs) are well suited to this technique, as they have a saturated drain current independent of source-drain separation, thus leading to improved current uniformity despite inconsistencies in gap size. © 2013 IEEE.
Opoku C, Sporea R, Stolojan V, Silva R, Shkunov M (2015) Si Nanowire - Array Source Gated Transistors,
Solution processed field-effect transistors based on single crystalline
silicon nanowires (Si NWs) with metal Schottky contacts are demonstrated. The
semiconducting layer was deposited from a nanowire ink formulation at room
temperature. The devices with 230nm thick SiO2 gate insulating layers show
excellent output current-voltage characteristics with early saturation voltages
under 2 volts, constant saturation current and exceptionally low dependence of
saturation voltage with the gate field. Operational principles of these devices
are markedly different from traditional ohmic-contact field-effect transistors
(FETs), and are explained using the source-gated transistor (SGT) concept in
which the semiconductor under the reverse biased Schottky source barrier is
depleted leading to low voltage pinch-off and saturation of drain current.
Device parameters including activation energy are extracted at different
temperatures and gate voltages to estimate the Schottky barrier height for
different electrode materials to establish transistor performance - barrier
height relationships. Numerical simulations are performed using 2D thin-film
approximation of the device structures at various Schottky barrier heights.
Without any adjustable parameters and only assuming low p-doping of the
transistor channel, the modelled data show exceptionally good correlation with
the measured data. From both experimental and simulation results, it is
concluded that source-barrier controlled nanowire transistors have excellent
potential advantages compared with a standard FET including mitigation of
short-channel effects, insensitivity in device operating currents to device
channel length variation, higher on/off ratios, higher gain, lower power
consumption and higher operational speed for solution processable and printable
nanowire electronics.
Sporea RA, Georgakopoulos S, Xu X, Guo X, Shkunov M, Shannon JM, Silva SRP (2013) Leveraging contact effects for field-effect transistor technologies with reduced complexity and superior current uniformity, Materials Research Society Symposium Proceedings 1553
In order to achieve high performance, the design of devices for large-area electronics needs to be optimized despite material or fabrication shortcomings. In numerous emerging technologies thin-film transistor (TFT) performance is hindered by contact effects. Here, we show that contact effects can be used constructively to create devices with performance characteristics unachievable by conventional transistor designs. Source-gated transistors (SGTs) are not designed with increasing transistor speed, mobility or sub-threshold slope in mind, but rather with improving certain aspects critical for real-world large area electronics such as stability, uniformity, power efficiency and gain. SGTs can achieve considerably lower saturation voltage and power dissipation compared to conventional devices driven at the same current; higher output impedance for over two orders of magnitude higher intrinsic gain; improved bias stress stability in amorphous materials; higher resilience to processing variations; current virtually independent of source-drain gap, source-gate overlap and semiconductor thickness variations. Applications such as amplifiers and drivers for sensors and actuators, low cost large area analog or digital circuits could greatly benefit from incorporating the SGT architecture. Copyright © Materials Research Society 2013.
Sporea DG, Sporea RA (2003) Integrated software package for laser diodes characterization, Proceedings of SPIE - The International Society for Optical Engineering 5227 pp. 464-471
The characteristics of laser diodes (wavelength of the emitted radiation, output optical power, embedded photodiode photocurrent, threshold current, serial resistance, external quantum efficiency) are strongly influenced by their driving circumstances (forward current, case temperature). In order to handle such a complex investigation in an efficient and objective manner, the operation of several instruments (a laser diode driver, a temperature controller, a wavelength meter, a power meter, and a laser beam analyzer) is synchronously controlled by a PC, through serial and GPIB communication. For each equipment, instruments drivers were designed using the industry standards graphical programming environment - Lab VIEW from National Instruments. All the developed virtual instruments operate under the supervision of a managing virtual instrument, which sets the driving parameters for each unit under test. The manager virtual instrument scans as appropriate the driving current and case temperature values for the selected laser diode. The software enables data saving in Excel compatible files. In this way, sets of curves can be produced according to the testing cycle needs.
Cui Q, Sporea RA, Liu W, Guo X (2014) Analytical Models for Delay and Power Analysis of Zero-[Formula: see text] Load Unipolar Thin-Film Transistor Logic Circuits, IEEE Transactions on Electron Devices
In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero- V-load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this paper, the analytical models for delay and power were developed for zero- V-load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero- V-load logic circuits.
Sporea RA, Trainor MJ, Young ND, Guo X, Shannon JM, Silva SRP (2011) Performance trade-offs in polysilicon source-gated transistors, Solid-State Electronics 65-66 (1) pp. 246-249
Self-aligned Schottky-source source-gated transistors (SGTs) have been made in polysilicon. The structures enable a direct comparison to be made between a SGT and a standard thin-film field-effect transistor (FET) on the same device. SGTs having excellent characteristics have been fabricated, with intrinsic gains approaching 10,000. The effects of bulk doping in the polysilicon and of the source barrier modification implant are considered in the context of the electrical output characteristics. It is shown that the choice of source length is a tradeoff between device speed and variations in current output due to variability during fabrication. © 2011 Elsevier Ltd. All rights reserved.
Shannon JM, Sporea RA, Georgakopoulos S, Shkunov M, Silva SRP (2013) Low-Field Behavior of Source-Gated Transistors, IEEE Transactions on Electron Devices
A physical description of low-field behavior of a Schottky source-gated transistor (SGT) is outlined where carriers crossing the source barrier by thermionic emission are restricted by JFET action in the pinch-off region at the drain end of the source. This mode of operation leads to transistor characteristics with low saturation voltage and high output impedance without the need for field relief at the edge of the Schottky source barrier and explains many characteristics of SGT observed experimentally. 2-D device simulations with and without barrier lowering due to the Schottky effect show that the transistors can be designed so that the current is independent of source length and thickness variations in the semiconductor. This feature together with the fact that the current in an SGT is independent of source-drain separation hypothesizes the fabrication of uniform current sources and other large-area analog circuit blocks with repeatable performance even in imprecise technologies such as high-speed printing.
Sporea RA, Guo X, Shannon JM, Silva SRP (2009) Effects of process variations on the current in Schottky Barrier Source-Gated Transistors, Proceedings of the International Semiconductor Conference (CAS) 2 pp. 413-416 IEEE
The sensitivity of the drain current in Schottky barrier source-gated transistors to process variation is studied using computer simulations. It is shown that provided the device is designed correctly, the current is independent of source-drain separation and is insensitive to source length variations. However, uniform insulator thickness and precise control of the source barrier is needed if good current uniformity is to be obtained.
Xu X, Sporea RA, Guo X (2013) Source-Gated Transistors for Power- and Area-Efficient AMOLED Pixel Circuits, IEEE Journal of Display Technology
Sporea RA, Overy M, Shannon JM, Silva SRP (2015) Temperature dependence of the current in Schottky-barrier source-gated transistors, Journal of Applied Physics 117 (18)
© 2015 AIP Publishing LLC.The temperature dependence of the drain current is an important parameter in thin-film transistors. In this paper, we propose that in source-gated transistors (SGTs), this temperature dependence can be controlled and tuned by varying the length of the source electrode. SGTs comprise a reverse biased potential barrier at the source which controls the current. As a result, a large activation energy for the drain current may be present which, although useful in specific temperature sensing applications, is in general deleterious in many circuit functions. With support from numerical simulations with Silvaco Atlas, we describe how increasing the length of the source electrode can be used to reduce the activation energy of SGT drain current, while maintaining the defining characteristics of SGTs: low saturation voltage, high output impedance in saturation, and tolerance to geometry variations. In this study, we apply the dual current injection modes to obtain drain currents with high and low activation energies and propose mechanisms for their exploitation in future large-area integrated circuit designs.
Jayawardena KDGI, Li S, Sam LF, Smith CTG, Beliatis MJ, Gandhi KK, Prabhath MRR, Pozegic TR, Chen S, Xu X, Dabera GDMR, Rozanski LJ, Sporea RA, Mills CA, Guo X, Silva SRP High efficiency air stable organic photovoltaics with an aqueous inorganic contact, ROYAL SOC CHEMISTRY
Sporea RA, Shannon JM, Silva SRP (2012) Modes of operation and optimum design for application of source-gated transistors, ECS Transactions 50 (8) pp. 65-70
We show that the source-gated transistor has two distinct modes of operation. In the low-field mode, the current from the reversebiased source barrier is restricted by the depleted semiconductor at the drain end of the source. In the high-field mode, the current depends on field-dependent barrier lowering in the same region of the source. In practice, both these modes usually occur: the former at low VG, the latter at high VG. It is shown that this understanding enables us to design devices in which the current is insensitive to large changes in structure and geometry. © The Electrochemical Society.
Sporea DG, Sporea RA (2005) Setup for the in situ monitoring of the irradiation-induced effects in optical fibers in the ultraviolet-visible optical range, Review of Scientific Instruments 76 (11) pp. 1-5
The paper describes a setup for in situ monitoring of the radiation-induced optical absorption and the radiation-induced luminescence, in the UV-visible spectral range (200-800 nm), for large diameter (400 ¼m) optical fibers. Silica and sapphire optical fibers were irradiated, at room temperature, with gamma rays (dose rate of 0.33 kGyh, total dose of 34.5 kGy) and protons (dose rate of 100 Gys, total dose of 1.8 MGy). At several moments, the irradiation was interrupted and the annealing of the radiation-induced optical absorption was observed at room temperature. The setup also makes possible the monitoring of the optical radiation-induced recovery of the optical absorption (the effect of photobleaching), as the optical fiber can be exposed at the same time to both the ionizing radiation (gamma or protons) and to the radiation of a broadband optical source. The optical absorption and radioluminescence were measured with an optical fiber multichannel spectrometer coupled to an optical fiber multiplexer. The equipment control as well as the data collection and processing were performed using the graphical programming environment LabVIEW. The paper includes several graphs illustrating the evolution of the optical absorption and radiation-induced luminescence during gamma and proton irradiation of optical fibers. © 2005 American Institute of Physics.
Sporea RA, Guo X, Shannon JM, Silva SRP (2010) Polysilicon source-gated transistors for mixed-signal systems-on-panel, Electrochemical Society - 218th ECS Meeting Abstracts 2010, MA 2010-02 3 pp. 1834-1834
Sporea RA, Shannon JM, Silva SRP (2011) High-resolution temperature sensing with source-gated transistors, Device Research Conference (DRC), 2011 69th Annual pp. 61-62 IEEE
Source-gated transistors (SGTs) are three-terminal devices in which the current is controlled by a potential barrier at the source. The gate voltage is used primarily to modulate the effective height of the source barrier. These devices have a number of operational advantages over conventional field-effect transistors, including a potentially much smaller saturation voltage and very low output conductance in saturation, which lead to low power operation and high intrinsic gain.
Cui Q, Sporea RA, Liu W, Guo X (2014) Analytical models for delay and power analysis of zero-VGS load unipolar thin-film Transistor Logic Circuits, IEEE Transactions on Electron Devices 61 (11) pp. 3838-3844
© 2014 IEEE.In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero-VGS-load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this paper, the analytical models for delay and power were developed for zero-VGS-load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero-VGS-load logic circuits.
Cui Q, Si M, Sporea RA, Guo X (2013) Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits, IEEE TRANSACTIONS ON ELECTRON DEVICES 60 (5) pp. 1782-1785 IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC