Dr Radu Sporea SMIEEE

Senior Lecturer in Semiconductor Devices
+44 (0)1483 686086
28 ATI 02
by email appointment


Areas of specialism

Electronic devices and circuits; Flexible and printed electronics; Manufacturability and reliability of electronics; Modelling and simulation; Unconventional electronics

Business, industry and community links



Research interests


Postgraduate research supervision

My teaching

My publications


EVA BESTELINK, Hao-Jing Teng, RADU A SPOREA (2021)Contact Doping as a Design Strategy for Compact TFT-Based Temperature Sensing, In: IEEE Transactions on Electron Devices Institute of Electrical and Electronics Engineers (IEEE)

Contact-controlled devices, such as source-gated transistors (SGTs), deliberately use energy barriers at the source, and naturally, the positive temperature dependence (PTD) of drain current can be utilized for temperature sensing. We exploit the difference in drain current activation energy, which arises with contact doping in polysilicon n-type contact-controlled transistors, to demonstrate output current with either a PTD or negative temperature dependence (NTD). The range over which output current varies linearly with temperature, as well as the sensitivity, can be tailored by the choice of reference current magnitude and relative source contact properties within the current mirror. The sensing scheme simplifies the circuit design because it relies solely on thin-film transistors and it has inherent immunity to output voltage variation. This ability to tune the sign of temperature dependence allows facile integration in applications requiring homeostasis via feedback, e.g., electronic skin, in a minimal layout area and potentially with convenient reduction of patterning steps during fabrication.

EVA BESTELINK, Olivier de Sagazan, Lea Motte, RADU A SPOREA (2021)Suppression of Hot-Carrier Effects Facilitated by the Multimodal Thin-Film Transistor Architecture, In: Advanced Electronic Materials2100533 Wiley

Hot-carrier effects are a persistent challenge for Ohmic contact, high carrier mobility thin-film transistors. As semiconductor properties are systematically improved, such phenomena (e.g., the kink effect) are becoming apparent even in materials such as InGaZnO. Few of the past solutions are practical in these low-complexity semiconductor systems. Here, it is shown that contact-controlled devices offer robust performance under extreme biasing conditions due to their distinctive charge injection processes. The recently-developed multimodal transistor (MMT) provides further control still, by separate regulation of current flow and magnitude. Internal electric field distributions in the source and drain regions are studied via technology computer-aided design simulations, and support the formulation of operational guidelines for the MMT's channel control gate for optimal characteristics in saturation. As MMT principles are universal, these findings should inform device design and operation in all high carrier mobility material systems.

EVA BESTELINK, Olivier de Sagazan, Isin Surekcigil Pesch, RADU A SPOREA (2021)Compact Unipolar xnor/xor Circuit Using Multimodal Thin-Film Transistors, In: IEEE Transactions on Electron Devices Institute of Electrical and Electronics Engineers (IEEE)

A novel compact realization of the xnor/xor function is demonstrated with multimodal transistors (MMTs). The multimodal thin-film transistors (MMT's) structure allows efficient use of layout area in an implementation optimized for unipolar thin-film transistor (TFT) technologies, which may serve as a multipurpose element for conventional and emerging large-area electronics. Microcrystalline silicon device fabrication is complemented by physical simulations.

AS Dahiya, C Opoku, RA Sporea, B Sarvankumar, G Poulin-Vittrant, F Cayrel, N Camara, D Alquier (2016)Single-crystalline ZnO sheet Source-Gated Transistors, In: Scientific Reports619232pp. ?-? Nature Publishing Group

Due to their fabrication simplicity, fully compatible with low-cost large-area device assembly strategies, source-gated transistors (SGTs) have received significant research attention in the area of high-performance electronics over large area low-cost substrates. While usually based on either amorphous or polycrystalline silicon (α-Si and poly-Si, respectively) thin-film technologies, the present work demonstrate the assembly of SGTs based on single-crystalline ZnO sheet (ZS) with asymmetric ohmic drain and Schottky source contacts. Electrical transport studies of the fabricated devices show excellent field-effect transport behaviour with abrupt drain current saturation (IDSSAT) at low drain voltages well below 2 V, even at very large gate voltages. The performance of a ZS based SGT is compared with a similar device with ohmic source contacts. The ZS SGT is found to exhibit much higher intrinsic gain, comparable on/off ratio and low off currents in the sub-picoamp range. This approach of device assembly may form the technological basis for highly efficient low-power analog and digital electronics using ZnO and/or other semiconducting nanomaterial.

RA Sporea, S Lygo-Baker (2016)Summer Research Placements - State-of-the-Art Science by pre-University Students, In: MRS AdvancesMRSF15-232

Summer research placements are an effective training and research tool. Over three years, our group has hosted nine pre-university students over periods of four to six weeks. Apart from student training and skills acquisition, the placements have produced several peer-reviewed technical publications. Our approach relies on careful pre-planning of activities, frequent student interaction, coupled with independent and group learning. We explore the advantages and disadvantages of this manner of running summer placements.

RA Sporea, JM Shannon, SRP Silva, X Guo (2017)Source-gated transistors for improved current-mode pixel drivers

Emissive displays require high-efficiency linear drivers which are stable under electrical stress and can deliver uniform performance across a large area. Owing to their low saturation voltage and flat saturation characteristic, source-gated transistors (SGTs) are ideally suited to act as power-efficient driving transistors in active matrix backplanes for lighting, low-power signage and display screens. It is shown that SGTs are also very stable during electrical stress. The technology is compatible with standard TFT fabrication allowing FET and SGT devices to be integrated in the same design and fabrication run.

RA Sporea, X Guo, JM Shannon, SRP Silva (2010)Polysilicon source-gated transistors for mixed-signal systems-on-panel, In: ECS Transactions33(5)pp. 419-424 Electrochemical Society

The performance benefits of using source-gated transistors (SGTs) in analog large-area electronic circuits are examined practically and via numerical simulations. In current mirror circuits made using thin-film technology, significant advantages are observed for SGT implementations. A comparison of current mirrors implemented with standard field effect transistors (FETs) and SGTs shows that the SGT version can operate at a lower voltage and has larger output dynamic range for a given device geometry. The results are explained in relation to the saturation mechanisms of the SGT and are supported by experimental measurements of polysilicon devices.

RA Sporea, X Guo, JM Shannon, SRP Silva (2011)Source-Gated Transistors for Versatile Large Area Electronic Circuit Design and Fabrication, In: ECS Transactions37(1)pp. 57-63 The Electrochemical Society

Source-gated transistors (SGTs) comprise a blocking contact or potential barrier at the source, which control the current. The paper describes how SGTs can be optimized for particular applications and for specific semiconductor material systems. It is shown how the saturation voltage can be designed to be an order of magnitude smaller than in equivalent FETs to give power savings of over 50% for the same current output. The SGT also achieves a better saturation regime, with lower output conductance over a larger range of drain voltages. Flat-panel lighting, remote sensing and signal processing and large-area circuits made using inexpensive but imprecise patterning techniques are some of the applications which could benefit from incorporating these devices.

RA Sporea, MJ Trainor, ND Young, JM Shannon, SRP Silva (2010)Performance improvements in polysilicon source-gated transistors, In: DRC Conference Digestpp. 245-246

The source-gated transistor (SGT) is a new type of transistor in which the current is controlled by a potential barrier at the source and by a gate which modulates the effective height of the source barrier. It is an ideal device architecture to be used with the low mobility materials typically applied to large area electronics, as it provides low saturation voltages and high output impedances. Furthermore, the high internal fields and low concentration of excess carriers lead to higher speed and better stability compared with FETs, particularly in disordered, low mobility semiconductors. As such, the SGT is especially well suited to thin-film analog circuits.

RA Sporea, JM Shannon, SRP Silva (2011)High-resolution temperature sensing with source-gated transistors, In: Device Research Conference (DRC), 2011 69th Annualpp. 61-62 IEEE

Source-gated transistors (SGTs) are three-terminal devices in which the current is controlled by a potential barrier at the source. The gate voltage is used primarily to modulate the effective height of the source barrier. These devices have a number of operational advantages over conventional field-effect transistors, including a potentially much smaller saturation voltage and very low output conductance in saturation, which lead to low power operation and high intrinsic gain.

RA Sporea, JM Shannon, SRP Silva, MJ Trainor, ND Young (2010)Performance trade-offs in polysilicon source-gated transistors, In: Proceedings of the European Solid State Device Research Conference, ESSDERC 2010pp. 222-225

Self-aligned Schottky-source source-gated transistors (SGTs) have been made in polysilicon. The structures enable a direct comparison to be made between a SGT and a standard thin-film field-effect transistor (FET) on the same device. SGTs having excellent characteristics have been fabricated, with intrinsic gains approaching 10,000. The effects of bulk doping in the polysilicon and of the source barrier modification implant are considered in the context of the electrical output characteristics. It is shown that the choice of source length is a tradeoff between device speed and current uniformity.

RA Sporea, JM Shannon, SRP Silva (2010)Properties of source-gated transistors in polysilicon, In: 6th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2010

This paper describes some of the performance characteristics of self-aligned polysilicon Schottky Source- Gated Transistors (SGTs) made on glass by laser annealing of amorphous silicon. The threshold and Schottky barrier height are tuned by varying the dose of dopants in the bulk and under the source respectively. These devices are well suited for analog applications owing to their low saturation voltage, low drain field dependence of the current and intrinsic gain which is in excess of 1000 for well designed structures. Double drain operation leads to fT ≈100MHz for non-optimized devices. Index Terms— Source-Gated Transistor, polysilicon, analog

Radu A. Sporea, Kham M. Niang, Andrew J. Flewitt, S. Ravi P. Silva Silva (2019)Novel Tunnel-Contact-Controlled IGZO Thin-Film Transistors with High Tolerance to Geometrical Variability, In: Advanced Materials Wiley

For the first time, thin insulating layers are used to modulate a depletion region at the source of a thin-film transistor. Bottom contact, staggered electrode transistors fabricated using RFsputtered IGZO as the channel layer, with a 3 nm ALD Al2O3 layer between the semiconductor and Ni source-drain contacts show behaviours typical of source-gated transistors (SGTs): low saturation voltage (VD_SAT ~ 3V), change in VD_SAT with gate voltage of only 0.12 V/V and flat saturated output characteristics (small dependence of drain current on drain voltage). The transistors show high tolerance to geometry variations: saturated current changes only 0.15x for channel lengths between 2 - 50 μm, and only 2x for sourcegate overlaps between 9 - 45 μm. A higher than expected (5x) increase in drain current for a 30K change in temperature, similar to Schottky-contact SGTs, underlines a more complex device operation than previously theorised. Optimizations for increasing intrinsic gain and reducing temperature effects are discussed. These devices complete the portfolio of contactcontrolled transistors, comprising devices with: Schottky contacts, bulk barrier or heterojunctions, and now, tunnelling insulating layers. The findings should also apply to nanowire transistors, leading to new low-power, robust design approaches as large-scale fabrication techniques with sub-nanometre control mature.

Barbara Salonikidou, Takeda Yasunori, Brice Le Borgne, Jonathan England, Tokito Shizuo, Radu Sporea (2019)Toward Fully Printed Memristive Elements: a-TiO2 Electronic Synapse from Functionalized Nanoparticle Ink., In: ACS Applied Electronic Materials1(12)pp. 2692-2700 American Chemical Society

Electronic devices that emulate biofunctionalities, such as synaptic plasticity, present a promising route to versatile and energy-efficient neuromorphic computing systems. As the demand for rapid prototyping and environmentally friendly fabrication of such devices rises, there are significant incentives toward finding solutions for low-cost materials and flexible deposition techniques. The development of printed electronic devices is still at an infant stage, presenting a timely opportunity to investigate material robustness and routes to overcoming fabrication obstacles toward fully printed electronic synapses. In this work, a low-power, fully printed Ag (200 nm)/a-TiO2 (80 nm)/Ag (160 nm) memristive device is demonstrated. The first electrical characterization of early devices exhibits biomimetic properties with an indication of activity-dependent plasticity. The active material is derived from a simplified nanoparticle ink formulation developed in-house. The ink characterization confirms that the formulation fulfills the criteria for efficient jetting while exhibiting a dwell time of 4 months. Additionally, the common detrimental fabrication issues of layer cracks and control over uniformity here are both overcome. The ink optimization and the investigation of the electrical framework under which the memristive element responds synaptically present a favorable approach to alternative fabrication methods for future neuromorphic electronics.

RA Sporea, MJ Trainor, ND Young, JM Shannon, SRP Silva (2014)Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits, In: SCIENTIFIC REPORTS4ARTN 4pp. ?-? NATURE PUBLISHING GROUP
Q Cui, W Liu, X Guo, RA Sporea (2014)Analytical models for delay and power analysis of zero-V load unipolar thin-film Transistor Logic Circuits, In: IEEE Transactions on Electron Devices61(11)pp. 3838-3844 IEEE

In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero-V-load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this paper, the analytical models for delay and power were developed for zero-V-load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero-V-load logic circuits.

Radu A. Sporea, Luke J. Wheeler, Vlad Stolojan, S. Ravi P. Silva (2018)Towards manufacturing high uniformity polysilicon circuits through TFT contact barrier engineering, In: Scientific Reports Nature Research

Abstract The predicted 50 billion devices connected to the Internet of Things by 2020 has renewed interest in polysilicon technology for high performance new sensing and control circuits, in addition to traditional display usage. Yet, the polycrystalline nature of the material presents significant challenges when used in transistors with strongly scaled channel lengths due to non-uniformity in device performance. For these new applications to materialize as viable products, uniform electrical characteristics on large areas will be essential. Here, we report on the effect of deliberately engineered potential barrier at the source of polysilicon thin-film transistors, yielding highly-uniform on-current (

RA Sporea, S Georgakopoulos, M Shkunov, JM Shannon, SRP Silva, X Xu, X Guo (2013)Leveraging contact effects for field-effect transistor technologies with reduced complexity and superior current uniformity, In: MRS Online Proceedings Library1553

In order to achieve high performance, the design of devices for large-area electronics needs to be optimized despite material or fabrication shortcomings. In numerous emerging technologies thin-film transistor (TFT) performance is hindered by contact effects. Here, we show that contact effects can be used constructively to create devices with performance characteristics unachievable by conventional transistor designs. Source-gated transistors (SGTs) are not designed with increasing transistor speed, mobility or sub-threshold slope in mind, but rather with improving certain aspects critical for real-world large area electronics such as stability, uniformity, power efficiency and gain. SGTs can achieve considerably lower saturation voltage and power dissipation compared to conventional devices driven at the same current; higher output impedance for over two orders of magnitude higher intrinsic gain; improved bias stress stability in amorphous materials; higher resilience to processing variations; current virtually independent of source-drain gap, source-gate overlap and semiconductor thickness variations. Applications such as amplifiers and drivers for sensors and actuators, low cost large area analog or digital circuits could greatly benefit from incorporating the SGT architecture.

RA Sporea, MJ Trainor, ND Young, JM Shannon, SRP Silva (2010)Intrinsic gain in self-aligned polysilicon source-gated transistors, In: IEEE Transactions on Electron Devices57(10)pp. 2434-2439

Thin-film, self-aligned source-gated transistors (SGTs) have been made in polysilicon. The very high output impedance of this type of transistor makes it suited to analog circuits. Intrinsic voltage gains of greater than one thousand have been measured at particular drain voltages. The drain voltage dependence of the gain is explained based on the device physics of the source-gated transistor and the fact that pinch-off occurs at both the source and the drain. The results obtained from these devices, which are far from optimal, suggest that, with proper design, the source-gated transistor is well suited to a wide range of analog applications.

Eva Bestelink, Kham M. Niang, George Bairaktaris, Luca Maiolo, Francesco Maita, Kalil Ali, Andrew J. Flewitt, Ravi Silva, Radu Sporea (2020)Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors, In: IEEE Sensors Institute of Electrical and Electronics Engineers

Silicon-based digital electronics have evolved over decades through an aggressive scaling process following Moore’s law with increasingly complex device structures. Simultaneously, large-area electronics have continued to rely on the same field-effect transistor structure with minimal evolution. This limitation has resulted in less than ideal circuit designs, with increased complexity to account for shortcomings in material properties and process control. At present, this situation is holding back the development of novel systems required for printed and flexible electronic applications beyond the Internet of Things. In this work we demonstrate the opportunity offered by the source-gated transistor’s unique properties for low-cost, highly functional large-area applications in two extremely compact circuit blocks. Polysilicon common-source amplifiers show 49 dB gain, the highest reported for a twotransistor unipolar circuit. Current mirrors fabricated in polysilicon and InGaZnO have, in addition to excellent current copying performance, the ability to control the temperature dependence (degrees of positive, neutral or negative) of output current solely by choice of relative transistor geometry, giving further flexibility to the design engineer. Application examples are proposed, including local amplification of sensor output for improved signal integrity, as well as temperature-regulated delay stages and timing circuits for homeostatic operation in future wearables. Numerous applications will benefit from these highly competitive compact circuit designs with robust performance, improved energy efficiency and tolerance to geometrical variations: sensor front-ends, temperature sensors, pixel drivers, bias analog blocks and high-gain amplifiers.

RA Sporea, T Burridge, SRP Silva (2015)Self-Heating Effects In Polysilicon Source Gated Transistors, In: SCIENTIFIC REPORTS5ARTN 1pp. ?-? NATURE PUBLISHING GROUP
RA Sporea, MJ Trainor, ND Young, X Guo, JM Shannon, SRP Silva (2011)Performance trade-offs in polysilicon source-gated transistors, In: Solid-State Electronics65-66(1)pp. 246-249 Elsevier

Self-aligned Schottky-source source-gated transistors (SGTs) have been made in polysilicon. The structures enable a direct comparison to be made between a SGT and a standard thin-film field-effect transistor (FET) on the same device. SGTs having excellent characteristics have been fabricated, with intrinsic gains approaching 10,000. The effects of bulk doping in the polysilicon and of the source barrier modification implant are considered in the context of the electrical output characteristics. It is shown that the choice of source length is a tradeoff between device speed and variations in current output due to variability during fabrication.

RA Sporea, JM Shannon, SRP Silva (2012)Modes of operation and optimum design for application of source-gated transistors, In: ECS Transactions50(8)pp. 65-70

We show that the source-gated transistor has two distinct modes of operation. In the low-field mode, the current from the reversebiased source barrier is restricted by the depleted semiconductor at the drain end of the source. In the high-field mode, the current depends on field-dependent barrier lowering in the same region of the source. In practice, both these modes usually occur: the former at low VG, the latter at high VG. It is shown that this understanding enables us to design devices in which the current is insensitive to large changes in structure and geometry. © The Electrochemical Society.

RA Sporea, X Guo, JM Shannon, SRP Silva (2009)Effects of process variations on the current in Schottky Barrier Source-Gated Transistors, In: Proceedings of the International Semiconductor Conference (CAS)2pp. 413-416

The sensitivity of the drain current in Schottky barrier source-gated transistors to process variation is studied using computer simulations. It is shown that provided the device is designed correctly, the current is independent of source-drain separation and is insensitive to source length variations. However, uniform insulator thickness and precise control of the source barrier is needed if good current uniformity is to be obtained.

E. Bestelink, T. Landers, R. A. Sporea (2019)Turn-off mechanisms in thin-film source-gated transistors with applications to power devices and rectification, In: Applied Physics Letters114(18)pp. 182103-1 AIP Publishing

We describe the physics of the turn-off mechanism in source-gated transistors (SGTs), which is distinct from that of conventional thin-film field-effect transistors and allows significantly lower off currents, particularly in depletion-mode devices. The “n-type” SGT enters its off state when the potential applied across the semiconductor layer is decreased to low positive values or made negative through the applied gate bias, thus impeding charge injection from the source contact. Measurements on polysilicon devices were supported with TCAD simulations using Silvaco Atlas. Alongside the other known benefits of SGTs, including low saturation voltage, tolerance to process variations, and high intrinsic gain, the ability to efficiently block current at high negative gate voltages suggests that these devices would be ideal elements in emerging thin-film power management and rectification circuits.

C Opoku, R Sporea, V Stolojan, R Silva, M Shkunov (2015)Si Nanowire - Array Source Gated Transistors

Solution processed field-effect transistors based on single crystalline silicon nanowires (Si NWs) with metal Schottky contacts are demonstrated. The semiconducting layer was deposited from a nanowire ink formulation at room temperature. The devices with 230nm thick SiO2 gate insulating layers show excellent output current-voltage characteristics with early saturation voltages under 2 volts, constant saturation current and exceptionally low dependence of saturation voltage with the gate field. Operational principles of these devices are markedly different from traditional ohmic-contact field-effect transistors (FETs), and are explained using the source-gated transistor (SGT) concept in which the semiconductor under the reverse biased Schottky source barrier is depleted leading to low voltage pinch-off and saturation of drain current. Device parameters including activation energy are extracted at different temperatures and gate voltages to estimate the Schottky barrier height for different electrode materials to establish transistor performance - barrier height relationships. Numerical simulations are performed using 2D thin-film approximation of the device structures at various Schottky barrier heights. Without any adjustable parameters and only assuming low p-doping of the transistor channel, the modelled data show exceptionally good correlation with the measured data. From both experimental and simulation results, it is concluded that source-barrier controlled nanowire transistors have excellent potential advantages compared with a standard FET including mitigation of short-channel effects, insensitivity in device operating currents to device channel length variation, higher on/off ratios, higher gain, lower power consumption and higher operational speed for solution processable and printable nanowire electronics.

Raymond Drury, Eva Bestelink, Radu A. Sporea (2019)Simulation study of overlap capacitance in source-gated transistors for current-mode pixel drivers, In: IEEE Electron Device Letters Institute of Electrical and Electronics Engineers (IEEE)

Contrary to conventional design principles, currentdriven pixel drivers based on source-gated transistors (SGTs) achieve their optimal drive current and speed with a deliberate 5 -10μm gate-source overlap. Total pixel circuit area need not increase, as the additional device area can be compensated by reducing the pixel storage capacitor. Numerical simulations demonstrate the viability of SGTs for emissive pixel drivers and high gain, low power, robust circuits for emerging sensor arrays.

A. S Dahiya, Radu Sporea, G. Poulin-Vittrant, D. Alquier (2019)Stability evaluation of ZnO nanosheet based source-gated transistors, In: Scientific Reports9(1)

Semiconducting nanostructures are one of the potential candidates to accomplish low-temperature and solution-based device assembly processes for the fabrication of transistors that offer practical solutions toward realizing low-cost flexible electronics. Meanwhile, it has been shown that by introducing a contact barrier, in a specific transistor configuration, stable device operation can be achieved at much reduced power consumption. In this work, we investigate both one-dimensional ZnO nanowires (NWs) and two-dimensional nanosheets (NSs) for high performance and stable nano-transistors on conventional Si/SiO2 substrates. We have fabricated two variant of transistors based on nanoscale single-crystalline oxide materials: field-effect transistors (FETs) and source-gated transistors (SGTs). Stability tests are performed on both devices with respect to gate bias stress at three different regimes of transistor operation, namely off-state, on-state and sub-threshold state. While in the off-state, FETs shows comparatively better stability than SGTs devices, in both sub-threshold and on-state regimes of transistors, SGTs clearly exhibits better robustness against bias stress variability. The present investigation experimentally demonstrates the potential advantages of SGTs over FETs as driver transistor for AMOLEDs display circuits which require very high stability in OLED driving current.

JM Shannon, RA Sporea, S Georgakopoulos, M Shkunov, SRP Silva (2013)Low-Field Behavior of Source-Gated Transistors, In: IEEE Transactions on Electron Devices60(8)pp. 2444-2449 IEEE

A physical description of low-field behavior of a Schottky source-gated transistor (SGT) is outlined where carriers crossing the source barrier by thermionic emission are restricted by JFET action in the pinch-off region at the drain end of the source. This mode of operation leads to transistor characteristics with low saturation voltage and high output impedance without the need for field relief at the edge of the Schottky source barrier and explains many characteristics of SGT observed experimentally. 2-D device simulations with and without barrier lowering due to the Schottky effect show that the transistors can be designed so that the current is independent of source length and thickness variations in the semiconductor. This feature together with the fact that the current in an SGT is independent of source-drain separation hypothesizes the fabrication of uniform current sources and other large-area analog circuit blocks with repeatable performance even in imprecise technologies such as high-speed printing.

David M. Frohlich, Emily Corrigan-Kavanagh, Mirek Bober, Haiyue Yuan, Radu Sporea, Brice Le Borgne, Caroline Scarles, George Revill, Jan Van Duppen, Alan W. Brown, Megan Beynon (2019)The Cornwall a-book: An Augmented Travel Guide Using Next Generation Paper, In: The Journal of Electronic Publishing22(1) Michigan Publishing

Electronic publishing usually presents readers with book or e-book options for reading on paper or screen. In this paper, we introduce a third method of reading on paper-and-screen through the use of an augmented book (‘a-book’) with printed hotlinks than can be viewed on a nearby smartphone or other device. Two experimental versions of an augmented guide to Cornwall are shown using either optically recognised pages or embedded electronics making the book sensitive to light and touch. We refer to these as second generation (2G) and third generation (3G) paper respectively. A common architectural framework, authoring workflow and interaction model is used for both technologies, enabling the creation of two future generations of augmented books with interactive features and content. In the travel domain we use these features creatively to illustrate the printed book with local multimedia and updatable web media, to point to the printed pages from the digital content, and to record personal and web media into the book.

X Guo, R Sporea, JM Shannon, SRP Silva (2009)Down-scaling of thin-film transistors: Opportunities and design challenges, In: ECS Transactions22(1)pp. 227-238

With the ever-increasing demands for integration of advanced electronic functions into large-area electronics, down-scaling of thin-film transistors (TFTs) becomes very necessary. The key device operational issues associated with TFT scaling, including short-channel effects (SCEs) and self-heating, are considered in this paper. Device structure engineering approaches are introduced to suppress the SCEs for designing short-channel TFTs with excellent digital and analog performance. And electro-thermal simulation results show that the self-heating in TFTs will be much more significant than that in silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) due to the substrate of poor thermal conductivity. Enhancing the heat dissipation by placement of metal heat pipe in the cap dielectric layers is proved to be an effective way to deal with the heating issues.

EVA BESTELINK, Olivier de Sagazan, Lea Motte, Max Bateson, Benedikt Schultes, S RAVI PRADIP SILVA, RADU A SPOREA (2020)Versatile Thin‐Film Transistor with Independent Control of Charge Injection and Transport for Mixed Signal and Analog Computation, In: Advanced Intelligent Systems

New materials and optimized fabrication techniques have led to steady evolution in large area electronics, yet significant advances come only with new approaches to fundamental device design. The multimodal thin‐film transistor introduced here offers broad functionality resulting from separate control of charge injection and transport, essentially using distinct regions of the active material layer for two complementary device functions, and is material agnostic. The initial implementation uses mature processes to focus on the device's fundamental benefits. A tenfold increase in switching speed, linear input–output dependence, and tolerance to process variations enable low‐distortion amplifiers and signal converters with reduced complexity. Floating gate designs eliminate deleterious drain voltage coupling for superior analog memory or computing. This versatile device introduces major new opportunities for thin‐film technologies, including compact circuits for integrated processing at the edge and energy‐efficient analog computation.

DG Sporea, RA Sporea (2003)Integrated software package for laser diodes characterization, In: Proceedings of SPIE - The International Society for Optical Engineering5227pp. 464-471

The characteristics of laser diodes (wavelength of the emitted radiation, output optical power, embedded photodiode photocurrent, threshold current, serial resistance, external quantum efficiency) are strongly influenced by their driving circumstances (forward current, case temperature). In order to handle such a complex investigation in an efficient and objective manner, the operation of several instruments (a laser diode driver, a temperature controller, a wavelength meter, a power meter, and a laser beam analyzer) is synchronously controlled by a PC, through serial and GPIB communication. For each equipment, instruments drivers were designed using the industry standards graphical programming environment - Lab VIEW from National Instruments. All the developed virtual instruments operate under the supervision of a managing virtual instrument, which sets the driving parameters for each unit under test. The manager virtual instrument scans as appropriate the driving current and case temperature values for the selected laser diode. The software enables data saving in Excel compatible files. In this way, sets of curves can be produced according to the testing cycle needs.

DG Sporea, C Oproiu, RA Sporea (2004)Degradation of heterojunction laser diodes under electron beam irradiation, In: Proceedings of SPIE - The International Society for Optical Engineering5577(PART 2)pp. 808-817

We are reporting the investigation on the degradation of heterojunction laser diodes as they were subjected to electron beam irradiation. The research was done under the European Union's Fusion Programme, and targets the possible use of semiconductor lasers for remote sensing and robotics, under irradiation conditions. A total irradiation dose of 600 kGy was achieved at room temperature. The measurements were performed off-line using an automatic measuring set-up. Following each irradiation step, several characteristics of the laser diodes were monitored, as function of the driving current and the case temperature: the emitted optical power, the wavelength of the emitted radiation, the embedded photodiode current, the longitudinal and transversal mode structure, as well as the temporal behavior of all these parameters. For each irradiation dose, the laser diode serial resistance, threshold current, and quantum efficiency, and the photodiode responsivity were plotted for different operating conditions.

(2021)Printed Light Tags and the Magic Bookmark: Using light to augment paper objects, In: CHI '21 Extended Abstracts Association for Computing Machinery (ACM)

Paper books offer a unique physical feel, which supports the reading experience through enhanced browsing, bookmarking, freeform annotations, memory and reduced eye strain. In contrast, electronic solutions, such as tablets and e-readers, offer interactive links, updatable information, easier content sharing, and efficient collaboration. To combine the best aspects of paper and digital information for reading, we demonstrate two mechanisms for augmenting paper with light sensors that trigger digital links on a nearby smartphone. Light Tags on every page of a book are used in a first demonstration to identify which pages are open. These are replaced with an electronic Magic Bookmark in a second demonstration, avoiding the need to instrument every page.

Georgios Bairaktaris, Brice Le Borgne, Sirpa Nordman, Samuli Yrjänä, Vikram Turkani, Rudresh Gosh, Vahid Akhavan, Peter Bagge, Timo Turpela, David M Frohlich, Radu A Sporea (2020)78‐2: Using Physical Books as Interfaces to Digital Displays, In: SID International Symposium Digest of technical papers51(1)pp. 1159-1162

A new form of interaction with digital displays is described, using the pages and binding of a physical book as the interface. This leads to a form of augmented book, or a‐book, which can seamlessly trigger multimedia content on a nearby device using embedded light, pressure or touch sensors.

RA Sporea, JM Shannon, SRP Silva, MJ Trainor, ND Young (2012)Field plate optimization in low-power high-gain source-gated transistors, In: IEEE Transactions on Electron Devices59(8)pp. 2180-2186 IEEE

Source-gated transistors (SGTs) have potentially very high output impedance and low saturation voltages, which make them ideal as building blocks for high-performance analog circuits fabricated in thin-film technologies. The quality of saturation is greatly influenced by the design of the field-relief structure incorporated into the source electrode. Starting from measurements on self-aligned polysilicon structures, we show through numerical simulations how the field plate (FP) design can be improved. A simple source FP around 1 μm long situated several tens of nanometers above the semiconductor can increase the low-voltage intrinsic gain by more than two orders of magnitude and offers adequate tolerance to process variations in a moderately scaled thin-film SGT. © 2012 IEEE.

Brice Le Borgne, Siyi Liu, Xavier Morvan, Samuel Crand, Radu Alexandru Sporea, Nanshu Lu, Maxime Harnois (2019)Water Transfer Printing Enhanced by Water‐Induced Pattern Expansion: Toward Large‐Area 3D Electronics, In: Advanced Materials Technologies4(4)1800600pp. 1-9 Wiley

Perfectly wrapping planar electronics to complex 3D surfaces represents a major challenge in the manufacture of conformable electronics. Intuitively, thinner electronics are easier to conform to curved surfaces but they usually require a supporting substrate for handling. The water transfer printing (WTP) technology utilizes water surface tension to keep ultrathin electronics floating flat without supporting substrate, enabling their conformal transfer on 3D surfaces through a dipping process. In many cases, however, the size of the microfabricated electronics is much smaller than the target 3D surface. This work proposes that such mismatch in size can be overcome by leveraging stretchable electronics in WTP. Stretchable electronics are compliant to in‐plane stretch induced by water surface tension, hence can first self‐expand in water and then be transferred onto 3D objects. Uniaxial and biaxial expansion ranging from 41% to 166% has been achieved without any externally applied tension. The results demonstrate that expansion‐enhanced WTP is a promising fabrication process for conformable electronics on large 3D surfaces.

DG Sporea, RA Sporea, C Oproiu, I Vatǎ (2005)Comparative study of gamma-ray, neutron and electron beam irradiated index-guided laser diodes, In: Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS

The effect of gamma-ray, neutron and electron beam irradiation on index-guided laser diodes was investigated off-line. The laser diodes subjected to this evaluation were AlGaAs, low power (8 mW), single transversal mode lasers emitting in the near-IR. The diodes degradation was assessed up to the total gamma dose of 1.23 MGy, the total electron beam dose of 0.6 MGy, and to the neutron fluence of 1.2 × 1013 n/cm2. The electrical, optical and optoelectronic characteristics were studied. The major irradiation induced changes are related to the embedded photodiode responsivity, the laser threshold current and its external quantum efficiency.

The paper describes a setup for in situ monitoring of the radiation-induced optical absorption and the radiation-induced luminescence, in the UV-visible spectral range (200-800 nm), for large diameter (400 μm) optical fibers. Silica and sapphire optical fibers were irradiated, at room temperature, with gamma rays (dose rate of 0.33 kGyh, total dose of 34.5 kGy) and protons (dose rate of 100 Gys, total dose of 1.8 MGy). At several moments, the irradiation was interrupted and the annealing of the radiation-induced optical absorption was observed at room temperature. The setup also makes possible the monitoring of the optical radiation-induced recovery of the optical absorption (the effect of photobleaching), as the optical fiber can be exposed at the same time to both the ionizing radiation (gamma or protons) and to the radiation of a broadband optical source. The optical absorption and radioluminescence were measured with an optical fiber multichannel spectrometer coupled to an optical fiber multiplexer. The equipment control as well as the data collection and processing were performed using the graphical programming environment LabVIEW. The paper includes several graphs illustrating the evolution of the optical absorption and radiation-induced luminescence during gamma and proton irradiation of optical fibers. © 2005 American Institute of Physics.

Q Cui, M Si, Radu Sporea, X Guo (2013)Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits, In: IEEE TRANSACTIONS ON ELECTRON DEVICES60(5)pp. 1782-1785 IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
R. M. I. Bandara, K. D. G. I. Jayawardena, S. O. Adeyemo, S. J. Hinder, J. A. Smith, H. M. Thirimanne, N. C. Wong, F. M. Amin, B. G. Freestone, A. J. Parnell, D. G. Lidzey, H. J. Joyce, R. A. Sporea, S. R. P. Silva (2019)Tin(iv) dopant removal through anti-solvent engineering enabling tin based perovskite solar cells with high charge carrier mobilities, In: Journal of Materials Chemistry C Royal Society of Chemistry

We report the need for careful selection of anti-solvents for Sn-based perovskite solar cells fabricated through the commonly used anti-solvent method, compared to their Pb-based counterparts. This, in combination with the film processing conditions used, enables the complete removal of unwanted Sn4+ dopants, through engineering the anti-solvent method for Sn-based perovskites. Using a Cs0.05(FA0.83MA0.17)0.95Pb0.5Sn0.5I3 perovskite, charge carrier mobilities of 32 ± 3 cm2 V−1 s−1 (the highest reported for such systems through the optical-pump terahertz probe technique) together with ∼28 mA cm−2 short circuit current densities are achieved. A champion efficiency of 11.6% was obtained for solvent extraction using toluene (an 80% enhancement in efficiency compared to the other anti-solvents) which is further improved to 12.04% following optimised anti-solvent wash and thermal treatment. Our work highlights the importance of anti-solvents in managing defects for high efficiency low bandgap perovskite materials and develops the potential for all-perovskite tandem solar cells.

RA Sporea, AS Alshammari, S Georgakopoulos, J Underwood, M Shkunov, SRP Silva (2013)Micron-scale inkjet-assisted digital lithography for large-area flexible electronics, In: 2013 PROCEEDINGS OF THE EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC)pp. 280-283 IEEE
RA Sporea, JM Shannon, SRP Silva, MJ Trainor, ND Young, X Guo (2011)Performance trade-offs in polysilicon source-gated transistors, In: Solid-State Electronics65-66(1)pp. 246-249

Self-aligned Schottky-source source-gated transistors (SGTs) have been made in polysilicon. The structures enable a direct comparison to be made between a SGT and a standard thin-film field-effect transistor (FET) on the same device. SGTs having excellent characteristics have been fabricated, with intrinsic gains approaching 10,000. The effects of bulk doping in the polysilicon and of the source barrier modification implant are considered in the context of the electrical output characteristics. It is shown that the choice of source length is a tradeoff between device speed and variations in current output due to variability during fabrication. © 2011 Elsevier Ltd. All rights reserved.

Brice Le Borgne, Bo-Yan Chung, Mehmet O. Tas, Simon G. King, Maxime Harnois, Radu A. Sporea (2019)Eco-Friendly Materials for Daily-Life Inexpensive Printed Passive Devices: Towards “Do-It-Yourself” Electronics, In: Electronics8(6) MDPI

The need for the fabrication of a new generation of devices has developed with the next generation of ‘home’ engineers, which is resulting in an ever-increasing population interested in “do-it-yourself” electronics and the Internet of Things. However, this new trend should not be done at the expense of the environment. Almost all previous studies, related to the low-temperature processing of devices, fail to highlight the extent of the impact that the synthesis of these technologies have on both the environment and human health. In addition, the substrates typically used, are also often associated with major drawbacks such as a lack of biodegradability. In this paper, we fabricate a simple RC filter using various domestically available printing techniques, utilising readily available materials such as: carbon soots (carbon black) as an electric conductor, and egg white (albumen) as a dielectric. These devices have been fabricated on both polyethylene terephthalate (PET) and paper, which demonstrated the same performances on both substrates and revealed that recyclable substrates can be used without compromise to the devices’ performance. The filter was found to exhibit a cut-off frequency of 170 kHz, which made it suitable for high-frequency reception applications.

KDG Imalka Jayawardena, S Li, LF Sam, Christopher Smith, MJ Beliatis, KK Gandhi, MR Ranga Prabhath, TR Pozegic, S Chen, X Xu, DMR Dabera, LJ Rozanski, RA Sporea, Chris Mills, X Guo, S Silva (2015)High efficiency air stable organic photovoltaics with an aqueous inorganic contact, In: Nanoscale(34)pp. 14241-14247 The Royal Society of Chemistry

We report a ZnO interfacial layer based on an environmentally friendly aqueous precursor for organic photovoltaics. Inverted PCDTBT devices based on this precursor show power conversion efficiencies of 6.8–7%. Unencapsulated devices stored in air display prolonged lifetimes extending over 200 hours with less than 20% drop in efficiency compared to devices based on the standard architecture.

K.D.G.I. Jayawardena, R. M. I. Bandara, M. Monti, E. Butler-Caddle, T. Pichler, H. Shiozawa, Z. Wang, S. Jenatsch, S. J. Hinder, M. G. Masteghin, M. Patel, H.M. Thirimanne, W. Zhang, R.A. Sporea, J. Lloyd-Hughes, S.R.P. Silva (2019)Approaching the Shockley–Queisser limit for fill factors in lead–tin mixed perovskite photovoltaics, In: Journal of Materials Chemistry A8(2)pp. 693-705 The Royal Society of Chemistry

The performance of all solar cells is dictated by charge recombination. A closer to ideal recombination dynamics results in improved performances, with fill factors approaching the limits based on Shockley–Queisser analysis. It is well known that for emerging solar materials such as perovskites, there are several challenges that need to be overcome to achieve high fill factors, particularly for large area lead–tin mixed perovskite solar cells. Here we demonstrate a strategy towards achieving fill factors above 80% through post-treatment of a lead–tin mixed perovskite absorber with guanidinium bromide for devices with an active area of 0.43 cm2. This bromide post-treatment results in a more favorable band alignment at the anode and cathode interfaces, enabling better bipolar extraction. The resulting devices demonstrate an exceptional fill factor of 83%, approaching the Shockley–Queisser limit, resulting in a power conversion efficiency of 14.4% for large area devices.

RA Sporea, W Wright, JM Shannon, SRP Silva (2015)Bulk barrier source-gated transistors with improved drain current dynamic range and temperature coefficient, In: ECS Transactions67(1)pp. 91-96

© The Electrochemical Society.Source-gated thin-film transistors (SGTs) have remarkable properties related to low-voltage amplification, tolerance to process variation and electrical stability. They rely on a potential barrier at the source in their operation, and usually this barrier is realized through a Schottky contact. Here, we study SGTs with source barriers made by doping the source region of the semiconductor to form bulk unipolar diodes (BUD). A BUSGT can have much higher drain current with a lower activation energy, resulting in higher switching speed and improved transconductance. Barriers made via doping also provide a wider range of barrier heights compared with Schottky contacts. We discuss design parameters for BUSGTs and compare these devices with SBSGTs.

RA Sporea, JM Shannon, SRP Silva, M Trainor, N Young (2015)Temperature effects in complementary inverters made with polysilicon source-gated transistors, In: IEEE Transactions on Electron Devices62(5)pp. 1498-1503 IEEE

Through their high gain and low saturation voltage, source-gated transistors (SGTs) have applications in both analog and digital thin-film circuits. In this paper, we show how we can design SGT-based logic gates, which are practically unaffected by temperature variations. We discuss design characteristics, which ensure reliable operation in spite of SGT temperature dependence of drain current, and their implications for manufacturability and large signal operation.

RA Sporea, M Trainor, N Young, JM Shannon, SRP Silva (2015)Temperature Effects in Complementary Inverters Made With Polysilicon Source-Gated Transistors, In: Electron Devices, IEEE Transactions onPP(99)pp. 1-1 IEEE

Through their high gain and low saturation voltage, source-gated transistors (SGTs) have applications in both analog and digital thin-film circuits. In this paper, we show how we can design SGT-based logic gates, which are practically unaffected by temperature variations. We discuss design characteristics, which ensure reliable operation in spite of SGT temperature dependence of drain current, and their implications for manufacturability and large signal operation.

RA Sporea, M Overy, JM Shannon, SRP Silva (2015)Temperature dependence of the current in Schottky-barrier source-gated transistors, In: JOURNAL OF APPLIED PHYSICS117(18)ARTN 1pp. ?-? AMER INST PHYSICS