- Image / Video Processing Algorithms.
- Signal processing for real-time applications.
- Computational architectures.
- Power Consumption in Semiconductors.
- Expert Systems.
(PONs) imposed high performance requirements for network
equipment. Especially, the 10G transmitter designs of the office
equipment (OLT), the terminals and the network units (ONTs
and ONUs) become quite demanding because of the real-time
requirements for preparing a frame. The current paper introduces
a three layer architecture, scalable with respect to the
bandwidth and suitable to realize the transmitter of the XGPON
OLT/ONT/ONU elements. The architecture?s upper layer
decides what data packets will be transmitted. The second layer?s
microsequencer commands the lowest layer?s modules, which
produce and locally store all the data packets to be transmitted.
The three layer approach allows the architecture to be configured
and organized as either an OLT transmitter or an ONU/ONT
transmitter; and to be scalable and perform the functions of the
OLT at 10 Gbps and those of an ONU/ONT at 2.5 Gbps. The
implementation of a XG-PON ONU transmitter on Xilinx Virtex7
verifies the approach.
FME bases on an interpolation procedure to increase the resolution of any frame region by generating sub-pixels between the original pixels. Modern compression standards specify the exact filter to use in the Motion Compensation module allowing the encoder and the decoder to create and use identical reference frames. In particular, H.264/AVC specifies a 6-tap filter for computing the luma values of half-pixels and a low cost 2-tap filter for computing quarter-pixels. Even though it is common practice for encoder designers to integrate the standard 6-tap filter also in the Estimation module (before Compensation), the fact is that the interpolation technique used for detecting the displacements (not computing their residual) is an open choice following certain performance trade-offs.
Aiming at speeding up the Estimation, a process of considerably higher computational demand than the Compensation, this work builds on the potential to implement a lower complexity interpolation technique instead of the H.264 6-tap filter. We integrate in the Estimation module several distinct interpolation techniques not included in the H.264 standard, while keeping the standard H.264/AVC Compensation to measure their impact on the outcome of the prediction engine.
Related bibliography includes both ideas to avoid/replace the standard computations, as well as architecturestargeting the efficient implementation of the H.264 6-tap filtering procedure and the support of its increased memory requirements. To this end, we note that H.264 specifies a kernel with coefficients è1,?5,20,20,?5,1é to be multiplied with six consecutive pixels of the frame (either in column or row format). The resulting six products are accumulated and normalized for the generation of a single half-pixel (between 3 rd and 4 th tap). The operation must be r
case of aggressive spatial multiplexing, combined with requirements towards very low processing latency despite the frequency
plateauing of traditional processors, initiates a need to revisit the fundamental maximum-likelihood (ML) and, consequently, the
sphere-decoding (SD) detection problem. This work presents the design and VLSI architecture of MultiSphere; the first method to
massively parallelize the tree search of large sphere decoders in a nearly-concurrent manner, without compromising their
maximum-likelihood performance, and by keeping the overall processing complexity comparable to that of highly-optimized sequential
sphere decoders. For a 10 å 10 MIMO spatially multiplexed system with 16-QAM modulation and 32 processing elements, our
MultiSphere architecture can reduce latency by 29å against well-known sequential SDs, approaching the processing latency of linear
detection methods, without compromising ML optimality. In MIMO multicarrier systems targeting exact ML decoding, MultiSphere
achieves processing latency and hardware efficiency that are orders of magnitude improved compared to approaches employing one
SD per subcarrier. In addition, for 16å16 both ?hard?- and ?soft?-output MIMO systems, approximate MultiSphere versions are shown to
achieve similar error rate performance with state-of-the art approximate SDs having akin parallelization properties, by using only one
tenth of the processing elements, and to achieve up to approximately 9å increased energy efficiency.
potential of rapid prototyping and evaluation of breakthrough concepts that these platforms provide, our work builds upon the wellknown
OpenAirInterface codebase, extending it for advanced, previously unsupported modes towards large and massive MIMO such as non-codebook-based multi-user transmissions. We then develop an acceleration/profiling framework, through which we present finegrained
execution results for DSP operations. Incorporating the latest SIMD instructions, our acceleration framework achieves a unitary speedup of up to 10. Integrated into OpenAirInterface, it accelerates computationally expensive MIMO operations by up to 88% across tested modes. Besides resulting in a useful tool for the community, this work provides insight on runtime DSP complexity and the potential of modern x86 64 systems.
for Rapid Development, Profiling,
Validation and Testing, IEEE Access Institute of Electrical and Electronics Engineers
targeting significant enhancements from the spectrum, to user experience. Newly-defined air-interface
features, such as large number of base station antennas and computationally complex physical layer
approaches come with a non-trivial development effort, especially when scalability and flexibility need to
be factored in. In addition, testing those features without commercial, off-the-shelf equipment has a high
deployment, operational and maintenance cost. On one hand, industry-hardened solutions are inaccessible
to the research community due to restrictive legal and financial licensing. On the other hand, researchgrade
real-time solutions are either lacking versatility, modularity and a complete protocol stack, or, for
those that are full-stack and modular, only the most elementary transmission modes are on offer (e.g., very
low number of base station antennas). Aiming to address these shortcomings towards an ideal research
platform, this paper presents SWORD, a SoftWare Open Radio Design that is flexible, open for research,
low-cost, scalable and software-driven, able to support advanced large and massive Multiple-Input Multiple-
Output (MIMO) approaches. Starting with just a single-input single-output air-interface and commercial
off-the-shelf equipment, we create a software-intensive baseband platform that, together with an acceleration/
profiling framework, can serve as a research-grade base station for exploring advancements towards
future wireless systems and beyond.
- Georgis, Georgios, Thanos, Alexios, Filo, Marcin and Nikitopoulos, Konstantinos (2020) A DSP ACCELERATION FRAMEWORK FOR SOFTWARE-DEFINED RADIOS ON X86 64 In: IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) 2020, May 4 to 8, 2020, Barcelona, Spain.
- Georgis, Georgios, Filo, Marcin, Thanos, Alexios, Husmann, Christopher, De Luna Ducoing, Juan Carlos, Tafazolli, Rahim and Nikitopoulos, Konstantinos (2019) SWORD: Towards a Soft and Open Radio Design for Rapid Development, Profiling, Validation and Testing IEEE Access.
- Nikitopoulos, Konstantinos, Georgis, Georgios, Jayawardena, Chathura, Chatzipanagiotis, Daniil and Tafazolli, Rahim (2018) Massively Parallel Tree Search for High-Dimensional Sphere Decoders Transactions on Parallel and Distributed Systems.
- C. Husmann, G. Georgis, K. Nikitopoulos and K. Jamieson, "FlexCore: Massively Parallel and Flexible Processing for Large MIMO Access Points", 14th USENIX symposium on Networked Systems Design and Implementation (NSDI), March 2017.
- G. Georgis, K. Nikitopoulos and K. Jamieson, "Geosphere: an Exact Depth-First Sphere Decoder Architecture Scalable to Very Dense Constellations.", IEEE Access vol. 5, pp. 4233-4249, March 2017.
- G. Georgis, G. Lentaris and D. Reisis, "Reduced Complexity Super-Resolution for Low-Bitrate Video Compression", Circuits and Systems for Video Technology, IEEE Transactions on , vol.26, no.2, pp.332-345, Feb. 2016.
- G. Georgis, G. Lentaris and D. Reisis, "Acceleration Techniques and Evaluation on Multicore CPU, GPU and FPGA for Image Processing & Super-Resolution", Journal of Real-Time Image Processing, pp.1-28, Jul. 2016.
- G. Menoutis, A. Foteas, N. Liakopoulos, G. Georgis, D. Reisis and G. Synnefakis, "A Configurable Transmitter Architecture & Organization for XG-PON OLT/ONU/ONT Network Elements", Electronics Circuits and Systems, 22nd IEEE International Conference on, Cairo Egypt, December 2015.
- G. Georgis, G. Menoutis, D. Reisis, K. Tsakalis and A. B. Shafique, "Towards Real-Time Neuronal Connectivity Assessment: a Scalable Pipelined Parallel Generalized Partial Directed Coherence Engine", Electronics Circuits and Systems, 22nd IEEE International Conference on, Cairo Egypt, December 2015.
- G. Georgis, D. Reisis, P. Skordilakis, K. Tsakalis, A. B. Shafique, G. Chatzikonstantis, G. Lentaris, "Neuronal Connectivity Assessment for Epileptic Seizure Prevention: Parallelizing the Generalized Partial Directed Coherence on Many-Core Platforms", Embedded Computer Systems: Architectures, Modeling and Simulation, IEEE International Conference on, Samos Greece, July 2014.
- G. Georgis, Ch. Tzeranis, G. Synnefakis and D. Reisis, "FPGA Design of the Decoding Functions in the Physical Layer Adaptation Subsystem of the XG-PON Optical Network Unit/Terminal", Ph.D. Research in Microelectronics and Electronics, 10th IEEE International Conference on, Grenoble, France, July 2014 [Silver Leaf Award].
- G. Georgis, Ch. Tzeranis, G. Synnefakis and D. Reisis, "XG-PON Optical Network Unit Downstream FEC Design Based on Truncated Reed-Solomon Code", Electronics Circuits and Systems, 21st IEEE International Conference on, Marseille France, December 2014.
- G. Georgis, G. Lentaris and D. Reisis, "Single-Image Super-Resolution using Low-Complexity Adaptive Iterative Back-projection", Digital Signal Processing, 18th IEEE International Conference on, Santorini Greece, July 2013.
- G. Georgis, G. Lentaris and D. Reisis, "Low Complexity Interpolation Filters for Motion Estimation and Application to the H.264 Encoders", Design and Architectures for Digital Signal Processing, Chapter 6, G. Ruiz and J. A. Mitchell, InTech Publishing, pp.137-154, January 2013.
- K. Manolopoulos, A. Belias, G. Georgis, D. Reisis and E.G. Anasontzis, "Signal processing for deep-sea observatories with reconfigurable hardware", Electronics Circuits and Systems, 19th IEEE International Conference on,pp. 81-84, Seville Spain, December 2012.
- G. Georgis, G. Lentaris, and D. Reisis, "Study of interpolation filters for motion estimation with application in H.264/AVC encoders", Electronics Circuits and Systems, 18th IEEE International Conference on,pp. 9-12, Beirut Lebanon, December 2011.